Bug Summary

File:include/trg/trg/State.h
Warning:line 271, column 13
Branch condition evaluates to a garbage value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -O3 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name FrontEnd.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fdebug-compilation-dir=/data/b2soft/buildbot/development/build -fcoverage-compilation-dir=/data/b2soft/buildbot/development/build -resource-dir /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/lib/clang/21 -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/include/c++ -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/include/c++/x86_64-redhat-linux -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/include/c++/backward -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/include -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/include/python3.12 -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/include/CLHEP -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/include/Geant4 -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/include -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/include/root -isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/include/belle_legacy -I include/ -D _PACKAGE_="trg" -D G4UI_USE_TCSH -D RaveDllExport= -D HAS_SQLITE -D HAS_CALLGRIND -I include -I /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/include/libxml2 -internal-isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/bin/../lib64/gcc/x86_64-redhat-linux/15.2.0/../../../../include/c++ -internal-isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/bin/../lib64/gcc/x86_64-redhat-linux/15.2.0/../../../../include/c++/x86_64-redhat-linux -internal-isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/bin/../lib64/gcc/x86_64-redhat-linux/15.2.0/../../../../include/c++/backward -internal-isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/lib/clang/21/include -internal-isystem /usr/local/include -internal-isystem /cvmfs/belle.cern.ch/el9/externals/v02-04-00/Linux_x86_64/common/bin/../lib64/gcc/x86_64-redhat-linux/15.2.0/../../../../x86_64-redhat-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -Wno-missing-braces -Wno-unused-command-line-argument -std=c++20 -fdeprecated-macro -ferror-limit 19 -fgnuc-version=4.2.1 -fno-implicit-modules -fskip-odr-check-in-gmf -fcxx-exceptions -fexceptions -vectorize-loops -vectorize-slp -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /scan_build/2026-05-31-004316-385593-1 -x c++ trg/cdc/src/FrontEnd.cc

trg/cdc/src/FrontEnd.cc

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1/**************************************************************************
2 * basf2 (Belle II Analysis Software Framework) *
3 * Author: The Belle II Collaboration *
4 * *
5 * See git log for contributors and copyright holders. *
6 * This file is licensed under LGPL-3.0, see LICENSE.md. *
7 **************************************************************************/
8
9//-----------------------------------------------------------------------------
10// Description : A class to represent a CDC front-end board
11//-----------------------------------------------------------------------------
12
13#define TRG_SHORT_NAMES
14#define TRGCDC_SHORT_NAMES
15
16#include "trg/trg/Utilities.h"
17#include "trg/trg/Debug.h"
18#include "trg/trg/State.h"
19#include "trg/cdc/TRGCDC.h"
20#include "trg/cdc/FrontEnd.h"
21#include "trg/cdc/Wire.h"
22
23using namespace std;
24
25namespace Belle2 {
26
27 TRGCDCFrontEnd::TRGCDCFrontEnd(const std::string& name,
28 boardType type,
29 const TRGClock& systemClock,
30 const TRGClock& dataClock,
31 const TRGClock& userClockOutput)
32 : TRGBoard(name,
33 systemClock,
34 dataClock,
35 userClockOutput,
36 userClockOutput),
37 _type(type),
38 _isb(0),
39 _osb(0)
40 {
41
42 }
43
44 TRGCDCFrontEnd::~TRGCDCFrontEnd()
45 {
46 }
47
48 string
49 TRGCDCFrontEnd::version(void)
50 {
51 return ("TRGCDCFrontEnd version 0.01");
52 }
53
54 TRGCDCFrontEnd::boardType
55 TRGCDCFrontEnd::type(void) const
56 {
57 return _type;
58 }
59
60 int
61 TRGCDCFrontEnd::implementation(const TRGCDCFrontEnd::boardType& type,
62 ofstream& outfile)
63 {
64
65 //string cname = "UNKNOWN";
66 // if (_type == innerInside) {
67 outfile << "-- inner type" << endl;
68 string cname = "TRGCDCFrontEndInnerInside";
69 // }
70 // else {
71 // outfile << "-- outer type" << endl;
72 // cname = "TRGCDCFrontEndOuter";
73 // }
74
75 outfile << "--" << endl;
76 outfile << endl;
77 outfile << " component " << cname << endl;
78 // int err = implementationPort(type, outfile);
79 outfile << " end component;" << endl;
80
81 outfile << "--------------------------------------------------------------"
82 << endl;
83
84 outfile << "entity " << cname << "is" << endl;
85 int err = implementationPort(type, outfile);
86 outfile << "end " << cname << ";" << endl;
87 outfile << endl;
88 outfile << "architecture Behavioral of " << cname << " is" << endl;
89 outfile << " -- local" << endl;
90 outfile << endl;
91 outfile << "begin" << endl;
92 outfile << "end Behavioral;" << endl;
93
94 return err;
95 }
96
97 int
98 TRGCDCFrontEnd::implementationPort(const TRGCDCFrontEnd::boardType&,
99 ofstream& outfile)
100 {
101 outfile << " port (" << endl;
102
103 //...125MHz clock (TRG system clock)...
104 outfile << " -- 125MHz clock (TRG system clock)" << endl;
105 outfile << " clk : in std_logic;" << endl;
106
107 //...Coarse timing...
108 outfile << " -- Coarse timing (counter with 125MHz clock)" << endl;
109 outfile << " tmc : in std_logic_vector(0 to 12);" << endl;
110
111 //...Hit pattern...
112 outfile << " -- Hit pattern(48 bits for 48 wires)" << endl;
113 outfile << " ptn : in std_logic_vector(0 to 47);" << endl;
114
115 //...Fine timing for each wire...
116 outfile << " -- Fine timing within 125MHz clock" << endl;
117 for (unsigned i = 0; i < 48; i++) {
118 outfile << " w" << TRGUtilTRGUtilities::itostring(i)
119 << " : in std_logic_vector(0 to 3);" << endl;
120 }
121
122 //...Hit pattern output...
123 outfile << " -- Hit pattern output" << endl;
124 outfile << " hit : out std_logic_vector(0 to 47);" << endl;
125 outfile << " -- 4 bit fine timing for 16 priority wires" << endl;
126 outfile << " pri : out std_logic_vector(0 to 63);" << endl;
127 outfile << " -- 2 bit fine timing for the fastest hit in 16 TS"
128 << endl;
129 outfile << " fst : out std_logic_vector(0 to 31)" << endl;
130 outfile << " );" << endl;
131
132 return 0;
133 }
134
135 void
136 TRGCDCFrontEnd::push_back(const TRGCDCWire* a)
137 {
138 std::vector<const TRGCDCWire*>::push_back(a);
139 }
140
141 void
142 TRGCDCFrontEnd::dump(const string& message, const string& pre) const
143 {
144 TRGBoard::dump(message, pre);
145 }
146
147 void
148 TRGCDCFrontEnd::simulate(void)
149 {
150
151
152 //...Clear input signal bundle...
153 if (_isb) {
154 for (unsigned i = 0; i < _isb->size(); i++)
155 delete (* _isb)[i];
156 delete _isb;
157 }
158 if (_osb) {
159 for (unsigned i = 0; i < _osb->size(); i++)
160 delete (* _osb)[i];
161 delete _osb;
162 }
163
164 //...Clock...
165 const TRGClock& dClock = clockData();
166
167 //...Input from wires...
168 const unsigned nWires = size();
169 TRGSignalVector input(name() + "inputSignals", dClock);
170 for (unsigned i = 0; i < nWires; i++) {
171
172 //...This may be too expensive. There must be a class to hold pointers.
173 input += (* this)[i]->signal();
174 }
175
176 //...Make input signal bundle...
177 const string ni = name() + "InputSignalBundle";
178 _isb = new TRGSignalBundle(ni, dClock);
179
180 //...Create hit pattern bits...
181 TRGSignalVector* pattern = new TRGSignalVector(input);
182 pattern->clock(dClock);
183 pattern->name(name() + "@dataClock");
184 _isb->push_back(pattern);
185
186 // if (TRGDebug::level() > 1) {
187 // if (input.active()) {
188 // input.dump("", TRGDebug::tab());
189 // pattern->dump("", TRGDebug::tab());
190 // }
191 // }
192
193 // output wire hit info into a .log file
194 // ofstream wireinfo((name()+"_wireinfo.log").c_str());
195
196
197 //...Create Wire timing bits...
198 for (unsigned i = 0; i < nWires; i++) {
199
200 const TRGSignal& s = input[i];
201 const string n = s.name() + ":5bits";
202 TRGSignalVector* bit5 = new TRGSignalVector(n, dClock);
203
204 //...No hit case : only dummy data...
205 if (!(* pattern)[i].active()) {
206 TRGSignal sig0(n + "-0", dClock);
207 TRGSignal sig1(n + "-1", dClock);
208 TRGSignal sig2(n + "-2", dClock);
209 TRGSignal sig3(n + "-3", dClock);
210 TRGSignal sig4(n + "-4", dClock);
211 bit5->push_back(sig0);
212 bit5->push_back(sig1);
213 bit5->push_back(sig2);
214 bit5->push_back(sig3);
215 bit5->push_back(sig4);
216 }
217
218 //...Hit case...
219 else {
220
221 // wire hit info -> .log
222 /*
223 if (type() == innerInside) { wireinfo << endl << " #" << (i > 15 ? i - 16 : 99999 ) << " wire is hit" << endl; }
224 else { wireinfo << endl << " #" << i << " wire is hit" << endl; }
225 output << endl;
226 */
227
228 // s is wire signal which is hit.
229 const std::vector<int> timing = s.stateChanges();
230 const unsigned nStates = timing.size();
231 // Loop over all the changing timing.
232 for (unsigned j = 0; j < nStates; j++) {
233 const int pos = timing[j];
234
235 //...Look at leading edges only...
236 if (s.state(pos)) {
237 const double at = s.clock().absoluteTime(pos);
238 const int pos1 = dClock.position(at);
239 const double phase = dClock.phase(at);
240 const unsigned bits = unsigned(phase / (360. / 32.));
241
242 // cout << "at,phase,bits,pos1=" << at << "," << phase << ","
243 // << bits <<","<<pos1<< endl;
244
245 // Change priority timing from unsigned into SignalVector.
246 if (bit5->active()) {
247 for (unsigned k = 0; k < 5; k++) {
248 if ((bits >> k) & 1)
249 (*bit5)[k].set(pos1, pos1 + 1);
250 }
251 } else {
252 for (unsigned k = 0; k < 5; k++) {
253 const string n1 = n + "-" + TRGUtilities::itostring(k);
254 TRGSignal sig(n1, dClock);
255 if ((bits >> k) & 1)
256 sig.set(pos1, pos1 + 1);
257 (* bit5) += sig;
258 }
259 }
260
261
262 //wire info -> .log
263 /*
264 //timing = 00000 case:
265 if ( !(bit5->stateChanges()).size() ) {
266 output << "# of clk: " << pos1 << " (" << pos1*32 << " ns), signal vector: 0 0 0 0 0" << endl;
267 }
268
269 const std::vector<int> bit5_changetime = bit5->stateChanges();
270 std::vector<vector<int>> bit5_boolvector(bit5_changetime.size());
271 for (unsigned ch_t = 0; ch_t < bit5_changetime.size(); ch_t++) {
272
273 for (unsigned b = 0; b < bit5->size(); b++){
274 bit5_boolvector[ch_t].push_back( (bit5->state( bit5_changetime[ch_t])[b]) ? 1 : 0 );
275 }
276
277 wireinfo << "# of clk: " << bit5_changetime[ch_t] << " (" << dClock.absoluteTime(bit5_changetime[ch_t]) << " ns), signal vector: " ;
278
279 for (unsigned b = 0; b < bit5->size(); b++){
280 wireinfo << bit5_boolvector[ch_t][ bit5->size() - b - 1] << " " ;
281 }
282
283 wireinfo << endl;
284 }
285 */
286
287
288#ifdef TRG_DEBUG
289// bit5->dump("detail", TRGDebug::tab());
290#endif
291 }
292 }
293 }
294
295 _isb->push_back(bit5);
296 }
297
298 //...Data clock...
299 // Data clock position data is omitted. Is this problem?
300
301 //...Make output signal bundle...
302 const string no = name() + "OutputSignalBundle";
303 if (type() == innerInside)
304 _osb = new TRGSignalBundle(no,
305 dClock,
306 * _isb,
307 256,
308 TCFrontEndTRGCDCFrontEnd::packerInnerInside);
309 else if (type() == innerOutside)
310 _osb = new TRGSignalBundle(no,
311 dClock,
312 * _isb,
313 256,
314 TCFrontEndTRGCDCFrontEnd::packerInnerOutside);
315 else if (type() == outerInside)
316 _osb = new TRGSignalBundle(no,
317 dClock,
318 * _isb,
319 256,
320 TCFrontEndTRGCDCFrontEnd::packerOuterInside);
321 else if (type() == outerOutside)
322 _osb = new TRGSignalBundle(no,
323 dClock,
324 * _isb,
325 256,
326 TCFrontEndTRGCDCFrontEnd::packerOuterOutside);
327
328 if (TRGDebug::level() > 1) {
329 cout << TRGDebug::tab() << name() << " input bundle" << endl;
330 _isb->dump("", TRGDebug::tab() + " ");
331 cout << TRGDebug::tab() << name() << " output bundle" << endl;
332 _osb->dump("", TRGDebug::tab() + " ");
333 }
334 }
335
336 TRGState
337 TRGCDCFrontEnd::packerInnerInside(const TRGState& input)
338 {
339
340 //...Input should be 48 hit pattern and 48x5 timing, total 288 bits...
341 //
342 // Wire numbers and TS ID
343 //
344 // outside
345 //
346 // +--+--+--+--+- -+--+--+--+--+--+--+
347 // | 31 | 30 | .... | 18 | 17 | 16 |
348 // +--+--+--+--+--+- -+--+--+--+--+--+--+
349 // | 15 | 14 | .....| 2 | 1 | 0 |
350 // +--+--+--+--+--+- -+--+--+--+--+--+--+
351 // | x | x | .... | x | x | x |
352 // +--+--+--+--+- -+--+--+--+--+--+--+
353 //
354 // 15 14 .... 2 1 0 <- partial TS ID
355 //
356 // inside
357 //
358
359 //...Prepare a state for output...
360 TRGState s(32 + 16 * 5 + 16 + 16 * 5 + 1 * 5 + 43); // 1*5 for missing wire + 43 bits to fill to 256 bits
361
362 //...Set up bool array...
363 bool* b = new bool[input.size()];
364 input.copy2bool(b);
365
366 //...Naming...
367 const bool* const hitptn = & b[16]; // 16x2 = 32 bits
368 const bool* const timing[32] = {
369 & b[128], & b[133], & b[138], & b[143],
370 & b[148], & b[153], & b[158], & b[163],
371 & b[168], & b[173], & b[178], & b[183],
372 & b[188], & b[193], & b[198], & b[203],
373 & b[208], & b[213], & b[218], & b[223],
374 & b[228], & b[233], & b[238], & b[243],
375 & b[248], & b[253], & b[258], & b[263],
376 & b[268], & b[273], & b[278], & b[283]
377 };
378
379 //...Store hit pattern...
380 s.set(0, 32, hitptn);
381 unsigned p = 32;
382
383 //bool true_5[5] = {true, true, true, true, true};
384
385 //...Priority timing...
386 TRGState secondPriority(16);
387 for (unsigned i = 0; i < 16; i++) {
388
389 //...Priority cell...
390 if (hitptn[i]) {
391 s.set(p, 5, timing[i]);
392 }
393
394 //...Second priority cells...
395 else {
396
397 //...Right side edge...
398 if (i == 0) {
399 if (hitptn[16]) {
400 s.set(p, 5, timing[16]);
401 secondPriority.set(i, true);
402 } else {
403 // s.set(p, 5, true_5);
404 secondPriority.set(i, false);
405 }
406 }
407
408 //...Others...
409 else {
410
411 //...Both secondarys have hit...
412 if (hitptn[i + 15] && hitptn[i + 16]) {
413 const unsigned t0 = TRGState::toUnsigned(5, timing[15]);
414 const unsigned t1 = TRGState::toUnsigned(5, timing[16]);
415 if (t0 < t1) {
416 s.set(p, 5, timing[i + 15]);
417 secondPriority.set(i, false);
418 } else {
419 s.set(p, 5, timing[i + 16]);
420 secondPriority.set(i, true);
421 }
422 }
423
424 //...Secondary at right side...
425 else if (hitptn[i + 15]) {
426 s.set(p, 5, timing[i + 15]);
427 secondPriority.set(i, false);
428 }
429
430 //...Secondary at left side...
431 else if (hitptn[i + 16]) {
432 s.set(p, 5, timing[i + 16]);
433 secondPriority.set(i, true);
434 }
435
436 // No secondary case. No action
437 else {
438 //s.set(p, 5, true_5);
439 //secondPriority.set(i, true);
440 }
441 }
442 }
443
444 p += 5;
445 }
446
447 s.set(p, secondPriority);
448 p += 16;
449
450 //...Fastest timing...
451 for (unsigned i = 0; i < 16; i++) {
452
453 //...Right side edge...
454 if (i == 0) {
455 const bool h[2] = {hitptn[0], hitptn[16]};
456 const unsigned hh = TRGState::toUnsigned(2, h);
457 const unsigned t0 = TRGState::toUnsigned(5, timing[0]);
458 const unsigned t1 = TRGState::toUnsigned(5, timing[16]);
459
460 //...No hit case : no action
461 if (hh == 0) {
462 //s.set(p, 5, true_5);
463 }
464
465 //...One hit case...
466 else if (hh == 1) {
467 s.set(p, 5, timing[0]);
468 } else if (hh == 2) {
469 s.set(p, 5, timing[16]);
470 }
471
472 //...Two hit case...
473 else {
474 if (t0 <= t1)
475 s.set(p, 5, timing[0]);
476 else
477 s.set(p, 5, timing[16]);
478 }
479 }
480
481 //...Others...
482 else {
483 const unsigned i0 = i;
484 const unsigned i1 = i + 15;
485 const unsigned i2 = i + 16;
486 const bool h[3] = {hitptn[i0], hitptn[i1], hitptn[i2]};
487 const unsigned hh = TRGState::toUnsigned(3, h);
488 const unsigned t0 = TRGState::toUnsigned(5, timing[i0]);
489 const unsigned t1 = TRGState::toUnsigned(5, timing[i1]);
490 const unsigned t2 = TRGState::toUnsigned(5, timing[i2]);
491
492 //...No hit case : no action
493 if (hh == 0) {
494 //s.set(p, 5, true_5);
495 }
496
497 //...One hit case...
498 else if (hh == 1) {
499 // cout << "p=" << p << endl;
500 // cout << "one hit pri" << endl;
501 // s.dump("detail", "one hit pri ");
502 // s.subset(p, 5).dump("detail", "one hit pri ");
503 s.set(p, 5, timing[i0]);
504 // s.dump("detail", "one hit pri ");
505 // s.subset(p, 5).dump("detail", "one hit pri ");
506 } else if (hh == 2) {
507 // cout << "one hit sec0" << endl;
508 s.set(p, 5, timing[i1]);
509 } else if (hh == 4) {
510 // cout << "one hit sec1" << endl;
511 s.set(p, 5, timing[i2]);
512 }
513
514 //...Two hit case...
515 else if (hh == 3) {
516 if (t0 <= t1)
517 s.set(p, 5, timing[i0]);
518 else
519 s.set(p, 5, timing[i1]);
520 } else if (hh == 5) {
521 if (t0 <= t2)
522 s.set(p, 5, timing[i0]);
523 else
524 s.set(p, 5, timing[i2]);
525 } else if (hh == 6) {
526 if (t1 <= t2)
527 s.set(p, 5, timing[i1]);
528 else
529 s.set(p, 5, timing[i2]);
530 }
531
532 //...Three hit case...
533 else {
534 if ((t0 <= t1) && (t0 <= t2))
535 s.set(p, 5, timing[i0]);
536 else if (t1 <= t2)
537 s.set(p, 5, timing[i1]);
538 else
539 s.set(p, 5, timing[i2]);
540 }
541 }
542
543 p += 5;
544 }
545
546 //...Timing of missing wires on edge TS...
547 if (hitptn[31]) {
548 s.set(p, 5, timing[31]);
549 } else {
550 //s.set(p, 5, true_5);
551 }
552 // p+=5;
553
554 //...Debug...
555#ifdef TRG_DEBUG
556 // input.dump("detail", TRGDebug::tab() + "FrontEnd_II in ");
557 // s.dump("detail", TRGDebug::tab() + "FrontEnd_II out ");
558// unpackerInnerInside(input, s);
559#endif
560
561 //...Termination...
562 delete[] b;
563 return s;
564 }
565
566 TRGState
567 TRGCDCFrontEnd::packerInnerOutside(const TRGState& input)
568 {
569
570 //...Input should be 48 hit pattern and 48x5 timing, total 288 bits...
571 //
572 // Wire numbers and TS ID
573 //
574 // outside
575 //
576 // +--+--+--+--+- -+--+--+--+--+--+--+
577 // | 47 | 46 | .... | 34 | 33 | 32 |
578 // +--+--+--+--+--+- -+--+--+--+--+--+--+
579 // | 31 | 30 | ..... | 18 | 17 | 16 |
580 // +--+--+--+--+--+- -+--+--+--+--+--+--+
581 // | 15 | 14 | .... | 2 | 1 | 0 |
582 // +--+--+--+--+- -+--+--+--+--+--+--+
583 //
584 // 15 14 .... 2 1 0 <- partial TS ID
585 //
586 // inside
587 //
588
589 //...Prepare a state for output...
590 TRGState s(48 + 16 * 5 + 4 * 5 + 108); // 4*5 for missing area timings + 108 to fill to 256 bits
591
592 //...Set up bool array...
593 bool* b = new bool[input.size()];
594 input.copy2bool(b);
595
596 //...Naming...
597 const bool* const hitptn = & b[0]; // 16x3 = 48 bits
598 const bool* const timing[48] = {
599 & b[48], & b[53], & b[58], & b[63],
600 & b[68], & b[73], & b[78], & b[83],
601 & b[88], & b[93], & b[98], & b[103],
602 & b[108], & b[113], & b[118], & b[123],
603 & b[128], & b[133], & b[138], & b[143],
604 & b[148], & b[153], & b[158], & b[163],
605 & b[168], & b[173], & b[178], & b[183],
606 & b[188], & b[193], & b[198], & b[203],
607 & b[208], & b[213], & b[218], & b[223],
608 & b[228], & b[233], & b[238], & b[243],
609 & b[248], & b[253], & b[258], & b[263],
610 & b[268], & b[273], & b[278], & b[283]
611 };
612
613 //...Store hit pattern...
614 s.set(0, 48, hitptn);
615 unsigned p = 48;
616
617 //...Fastest timing...
618 const bool dummy[6] = {false, false, false, false, false, true},
619 dummymax[5] = {true, true, true, true, true};
620 const TRGState wtDummy(6, dummy), wtDummymax(5, dummymax);
621 for (unsigned i = 0; i < 20; i++) { // 0 ... 15 for 16 standard ones, 16...19 for four edge areas.
622 TRGState wt[12];
623
624 if (i == 0) { // TS ID 0 has missing wires
625 wt[0] = wtDummy;
626 wt[1] = TRGState(5, timing[0]);
627 wt[2] = TRGState(5, timing[1]);
628 wt[3] = wtDummy;
629 wt[4] = wtDummy;
630 wt[5] = TRGState(5, timing[16]);
631 wt[6] = TRGState(5, timing[17]);
632 wt[7] = wtDummy;
633 wt[8] = wtDummy;
634 wt[9] = TRGState(5, timing[32]);
635 wt[10] = TRGState(5, timing[33]);
636 wt[11] = TRGState(5, timing[34]);
637
638 //...Append 6th bit to indicate hit or not (no hit = 1)...
639 if (! hitptn[0]) wt[1].set(5, true);
640 if (! hitptn[1]) wt[2].set(5, true);
641 if (! hitptn[16]) wt[5].set(5, true);
642 if (! hitptn[17]) wt[6].set(5, true);
643 if (! hitptn[32]) wt[9].set(5, true);
644 if (! hitptn[33]) wt[10].set(5, true);
645 if (! hitptn[34]) wt[11].set(5, true);
646 } else if (i == 1) { // TS ID 1 has missing wires
647 wt[0] = TRGState(5, timing[0]);
648 wt[1] = TRGState(5, timing[1]);
649 wt[2] = TRGState(5, timing[2]);
650 wt[3] = wtDummy;
651 wt[4] = TRGState(5, timing[16]);
652 wt[5] = TRGState(5, timing[17]);
653 wt[6] = TRGState(5, timing[18]);
654 wt[7] = wtDummy;
655 wt[8] = TRGState(5, timing[32]);
656 wt[9] = TRGState(5, timing[33]);
657 wt[10] = TRGState(5, timing[34]);
658 wt[11] = TRGState(5, timing[35]);
659
660 //...Append 6th bit to indicate hit or not (no hit = 1)...
661 if (! hitptn[0]) wt[0].set(5, true);
662 if (! hitptn[1]) wt[1].set(5, true);
663 if (! hitptn[2]) wt[2].set(5, true);
664 if (! hitptn[16]) wt[4].set(5, true);
665 if (! hitptn[17]) wt[5].set(5, true);
666 if (! hitptn[18]) wt[6].set(5, true);
667 if (! hitptn[32]) wt[8].set(5, true);
668 if (! hitptn[33]) wt[9].set(5, true);
669 if (! hitptn[34]) wt[10].set(5, true);
670 if (! hitptn[35]) wt[11].set(5, true);
671 } else if (i == 14) { // TS ID 14 has missing wires
672 wt[0] = TRGState(5, timing[13]);
673 wt[1] = TRGState(5, timing[14]);
674 wt[2] = TRGState(5, timing[15]);
675 wt[3] = TRGState(5, timing[28]);
676 wt[4] = TRGState(5, timing[29]);
677 wt[5] = TRGState(5, timing[30]);
678 wt[6] = TRGState(5, timing[31]);
679 wt[7] = TRGState(5, timing[44]);
680 wt[8] = TRGState(5, timing[45]);
681 wt[9] = TRGState(5, timing[46]);
682 wt[10] = TRGState(5, timing[47]);
683 wt[11] = wtDummy;
684
685 //...Append 6th bit to indicate hit or not (no hit = 1)...
686 if (! hitptn[13]) wt[0].set(5, true);
687 if (! hitptn[14]) wt[1].set(5, true);
688 if (! hitptn[15]) wt[2].set(5, true);
689 if (! hitptn[28]) wt[3].set(5, true);
690 if (! hitptn[29]) wt[4].set(5, true);
691 if (! hitptn[30]) wt[5].set(5, true);
692 if (! hitptn[31]) wt[6].set(5, true);
693 if (! hitptn[44]) wt[7].set(5, true);
694 if (! hitptn[45]) wt[8].set(5, true);
695 if (! hitptn[46]) wt[9].set(5, true);
696 if (! hitptn[47]) wt[10].set(5, true);
697 } else if (i == 15) { // TS ID 15 has missing wires
698 wt[0] = TRGState(5, timing[14]);
699 wt[1] = TRGState(5, timing[15]);
700 wt[2] = wtDummy;
701 wt[3] = TRGState(5, timing[29]);
702 wt[4] = TRGState(5, timing[30]);
703 wt[5] = TRGState(5, timing[31]);
704 wt[6] = wtDummy;
705 wt[7] = TRGState(5, timing[45]);
706 wt[8] = TRGState(5, timing[46]);
707 wt[9] = TRGState(5, timing[47]);
708 wt[10] = wtDummy;
709 wt[11] = wtDummy;
710
711 //...Append 6th bit to indicate hit or not (no hit = 1)...
712 if (! hitptn[14]) wt[0].set(5, true);
713 if (! hitptn[15]) wt[1].set(5, true);
714 if (! hitptn[29]) wt[3].set(5, true);
715 if (! hitptn[30]) wt[4].set(5, true);
716 if (! hitptn[31]) wt[5].set(5, true);
717 if (! hitptn[45]) wt[7].set(5, true);
718 if (! hitptn[46]) wt[8].set(5, true);
719 if (! hitptn[47]) wt[9].set(5, true);
720 } else if (i == 16) { // edge area 1, only cell 32 at position 11
721 wt[0] = wtDummy;
722 wt[1] = wtDummy;
723 wt[2] = wtDummy;
724 wt[3] = wtDummy;
725 wt[4] = wtDummy;
726 wt[5] = wtDummy;
727 wt[6] = wtDummy;
728 wt[7] = wtDummy;
729 wt[8] = wtDummy;
730 wt[9] = wtDummy;
731 wt[10] = wtDummy;
732 wt[11] = TRGState(5, timing[32]);
733
734 //...Append 6th bit to indicate hit or not (no hit = 1)...
735 if (! hitptn[32]) wt[11].set(5, true);
736 } else if (i == 17) { // edge area 1, cell 0, 16, 32, 33 at position 2, 6, 10, 11
737 wt[0] = wtDummy;
738 wt[1] = wtDummy;
739 wt[2] = TRGState(5, timing[0]);
740 wt[3] = wtDummy;
741 wt[4] = wtDummy;
742 wt[5] = wtDummy;
743 wt[6] = TRGState(5, timing[16]);
744 wt[7] = wtDummy;
745 wt[8] = wtDummy;
746 wt[9] = wtDummy;
747 wt[10] = TRGState(5, timing[32]);
748 wt[11] = TRGState(5, timing[33]);
749
750 //...Append 6th bit to indicate hit or not (no hit = 1)...
751 if (! hitptn[0]) wt[2].set(5, true);
752 if (! hitptn[16]) wt[6].set(5, true);
753 if (! hitptn[32]) wt[10].set(5, true);
754 if (! hitptn[33]) wt[11].set(5, true);
755 } else if (i == 18) { // edge area 3, cell 15, 30, 31, 46, 47 at position 0, 3, 4, 7, 8
756 wt[0] = TRGState(5, timing[15]);
757 wt[1] = wtDummy;
758 wt[2] = wtDummy;
759 wt[3] = TRGState(5, timing[30]);
760 wt[4] = TRGState(5, timing[31]);
761 wt[5] = wtDummy;
762 wt[6] = wtDummy;
763 wt[7] = TRGState(5, timing[46]);
764 wt[8] = TRGState(5, timing[47]);
765 wt[9] = wtDummy;
766 wt[10] = wtDummy;
767 wt[11] = wtDummy;
768
769 //...Append 6th bit to indicate hit or not (no hit = 1)...
770 if (! hitptn[15]) wt[0].set(5, true);
771 if (! hitptn[30]) wt[3].set(5, true);
772 if (! hitptn[31]) wt[4].set(5, true);
773 if (! hitptn[46]) wt[7].set(5, true);
774 if (! hitptn[47]) wt[8].set(5, true);
775 } else if (i == 19) { // edge area 4, only cell 31 and 47 at position 3 and 7
776 wt[0] = wtDummy;
777 wt[1] = wtDummy;
778 wt[2] = wtDummy;
779 wt[3] = TRGState(5, timing[31]);
780 wt[4] = wtDummy;
781 wt[5] = wtDummy;
782 wt[6] = wtDummy;
783 wt[7] = TRGState(5, timing[47]);
784 wt[8] = wtDummy;
785 wt[9] = wtDummy;
786 wt[10] = wtDummy;
787 wt[11] = wtDummy;
788
789 //...Append 6th bit to indicate hit or not (no hit = 1)...
790 if (! hitptn[31]) wt[3].set(5, true);
791 if (! hitptn[47]) wt[7].set(5, true);
792 } else {
793 wt[0] = TRGState(5, timing[i - 1]);
794 wt[1] = TRGState(5, timing[i]);
795 wt[2] = TRGState(5, timing[i + 1]);
796 wt[3] = TRGState(5, timing[i + 14]);
797 wt[4] = TRGState(5, timing[i + 15]);
798 wt[5] = TRGState(5, timing[i + 16]);
799 wt[6] = TRGState(5, timing[i + 17]);
800 wt[7] = TRGState(5, timing[i + 30]);
801 wt[8] = TRGState(5, timing[i + 31]);
802 wt[9] = TRGState(5, timing[i + 32]);
803 wt[10] = TRGState(5, timing[i + 33]);
804 wt[11] = TRGState(5, timing[i + 34]);
805
806 //...Append 6th bit to indicate hit or not (no hit = 1)...
807 if (! hitptn[i - 1]) wt[0].set(5, true);
808 if (! hitptn[i]) wt[1].set(5, true);
809 if (! hitptn[i + 1]) wt[2].set(5, true);
810 if (! hitptn[i + 14]) wt[3].set(5, true);
811 if (! hitptn[i + 15]) wt[4].set(5, true);
812 if (! hitptn[i + 16]) wt[5].set(5, true);
813 if (! hitptn[i + 17]) wt[6].set(5, true);
814 if (! hitptn[i + 30]) wt[7].set(5, true);
815 if (! hitptn[i + 31]) wt[8].set(5, true);
816 if (! hitptn[i + 32]) wt[9].set(5, true);
817 if (! hitptn[i + 33]) wt[10].set(5, true);
818 if (! hitptn[i + 34]) wt[11].set(5, true);
819 }
820
821 //...Look for the fastest hit...
822 unsigned fastest0 = 0;
823 unsigned fastest1 = 0;
824 unsigned fastest2 = 0;
825 unsigned fastest3 = 0;
826 unsigned fastest4 = 0;
827 unsigned fastest5 = 0;
828 if (wt[0] < wt[1])
829 fastest0 = 0;
830 else
831 fastest0 = 1;
832 if (wt[2] < wt[3])
833 fastest1 = 2;
834 else
835 fastest1 = 3;
836 if (wt[4] < wt[5])
837 fastest2 = 4;
838 else
839 fastest2 = 5;
840 if (wt[6] < wt[7])
841 fastest3 = 6;
842 else
843 fastest3 = 7;
844 if (wt[8] < wt[9])
845 fastest4 = 8;
846 else
847 fastest4 = 9;
848 if (wt[10] < wt[11])
849 fastest5 = 10;
850 else
851 fastest5 = 11;
852
853 unsigned fastest10 = 0;
854 if (wt[fastest0] < wt[fastest1])
855 fastest10 = fastest0;
856 else
857 fastest10 = fastest1;
858
859 unsigned fastest11 = 0;
860 if (wt[fastest2] < wt[fastest3])
861 fastest11 = fastest2;
862 else
863 fastest11 = fastest3;
864
865 unsigned fastest12 = 0;
866 if (wt[fastest4] < wt[fastest5])
867 fastest12 = fastest4;
868 else
869 fastest12 = fastest5;
870
871 unsigned fastest101 = 0;
872 if (wt[fastest10] < wt[fastest11])
873 fastest101 = fastest10;
874 else
875 fastest101 = fastest11;
876
877 unsigned fastest102 = 0;
878 if (wt[fastest101] < wt[fastest12])
879 fastest102 = fastest101;
880 else
881 fastest102 = fastest12;
882
883 TRGState fastest(5);
884 if (! wt[fastest102].active(5))
885 fastest = wt[fastest102].subset(0, 5);
886
887 s.set(p, fastest);
888 p += 5;
889 }
890
891 ////...Timing of missing wires on edge TS...
892 //s.set(p, 5, timing[0]);
893 //p += 5;
894 //s.set(p, 5, timing[16]);
895 //p += 5;
896 //s.set(p, 5, timing[32]);
897 //p += 5;
898 //s.set(p, 5, timing[33]);
899 //p += 5;
900 //s.set(p, 5, timing[15]);
901 //p += 5;
902 //s.set(p, 5, timing[30]);
903 //p += 5;
904 //s.set(p, 5, timing[31]);
905 //p += 5;
906 //s.set(p, 5, timing[46]);
907 //p += 5;
908 //s.set(p, 5, timing[47]);
909
910#ifdef TRG_DEBUG
911// unpackerInnerOutside(input, s);
912#endif
913
914 delete[] b;
915 return s;
916 }
917
918 TRGState
919 TRGCDCFrontEnd::packerOuterInside(const TRGState& input)
920 {
921
922 //...Input should be 48 hit pattern and 48x5 timing, total 288 bits...
923 //
924 // Wire numbers and TS ID
925 //
926 // outside
927 //
928 // +--+--+--+--+- -+--+--+--+--+--+--+
929 // | 47 | 46 | .... | 34 | 33 | 32 | <- priority wire layer
930 // +--+--+--+--+--+- -+--+--+--+--+--+--+
931 // | 31 | 30 | ..... | 18 | 17 | 16 |
932 // +--+--+--+--+--+- -+--+--+--+--+--+--+
933 // | 15 | 14 | .... | 2 | 1 | 0 |
934 // +--+--+--+--+- -+--+--+--+--+--+--+
935 //
936 // 15 14 .... 2 1 0 <- partial TS ID
937 //
938 // inside
939 //
940 //
941
942 //...Prepare a state for output...
943 //TRGState s(48 + 16 * 5 + 16 * 5 + 3 * 5); // 3*5 for missing wires
944 TRGState s(48 + 16 * 5 + 16 * 5 + 2 * 5 + 38); // 2*5 for edge fastest time, 38 dummy bits to fill to 256 bits
945
946 //...Set up bool array...
947 bool* b = new bool[input.size()];
948 input.copy2bool(b);
949
950 //...Naming...
951 const bool* const hitptn = & b[0]; // 16x3 = 48 bits
952 const bool* const timing[48] = {
953 & b[48], & b[53], & b[58], & b[63],
954 & b[68], & b[73], & b[78], & b[83],
955 & b[88], & b[93], & b[98], & b[103],
956 & b[108], & b[113], & b[118], & b[123],
957 & b[128], & b[133], & b[138], & b[143],
958 & b[148], & b[153], & b[158], & b[163],
959 & b[168], & b[173], & b[178], & b[183],
960 & b[188], & b[193], & b[198], & b[203],
961 & b[208], & b[213], & b[218], & b[223],
962 & b[228], & b[233], & b[238], & b[243],
963 & b[248], & b[253], & b[258], & b[263],
964 & b[268], & b[273], & b[278], & b[283]
965 };
966
967 //...Store hit pattern...
968 s.set(0, 48, hitptn);
969 unsigned p = 48;
970
971 //...Priority cell timing...
972 for (unsigned i = 0; i < 16; i++) {
973 s.set(p, 5, timing[32 + i]);
974 p += 5;
975 }
976
977 //...Fastest timing...
978 const bool dummy[6] = {false, false, false, false, false, true};
979 const TRGState wtDummy(6, dummy);
980 for (unsigned i = 0; i < 18; i++) { // 0 ... 15 for 16 standard ones, 16,17 for two edge areas.
981 TRGState wt[6];
982
983 if (i == 0) { // TS ID 0 has missing wires
984 wt[0] = wtDummy;
985 wt[1] = TRGState(5, timing[0]);
986 wt[2] = TRGState(5, timing[1]);
987 wt[3] = wtDummy;
988 wt[4] = TRGState(5, timing[16]);
989 wt[5] = TRGState(5, timing[32]);
990
991 //...Append 6th bit to indicate hit or not (no hit = 1)...
992 if (! hitptn[0]) wt[1].set(5, true);
993 if (! hitptn[1]) wt[2].set(5, true);
994 if (! hitptn[16]) wt[4].set(5, true);
995 if (! hitptn[32]) wt[5].set(5, true);
996 } else if (i == 15) { // TS ID 15 has missing wires
997 wt[0] = TRGState(5, timing[14]);
998 wt[1] = TRGState(5, timing[15]);
999 wt[2] = wtDummy;
1000 wt[3] = TRGState(5, timing[30]);
1001 wt[4] = TRGState(5, timing[31]);
1002 wt[5] = TRGState(5, timing[47]);
1003
1004 //...Append 6th bit to indicate hit or not (no hit = 1)...
1005 if (! hitptn[14]) wt[0].set(5, true);
1006 if (! hitptn[15]) wt[1].set(5, true);
1007 if (! hitptn[30]) wt[3].set(5, true);
1008 if (! hitptn[31]) wt[4].set(5, true);
1009 if (! hitptn[47]) wt[5].set(5, true);
1010 } else if (i == 16) { // edge area 1 only for cell 0
1011 wt[0] = wtDummy;
1012 wt[1] = wtDummy;
1013 //wt[2] = TRGState(5, timing[16]);
1014 wt[2] = TRGState(5, timing[0]);
1015 wt[3] = wtDummy;
1016 wt[4] = wtDummy;
1017 wt[5] = wtDummy;
1018 //...Append 6th bit to indicate hit or not (no hit = 1)...
1019 if (! hitptn[0]) wt[2].set(5, true);
1020 } else if (i == 17) { // edge area 2 for cell 15 and 31 only
1021 wt[0] = TRGState(5, timing[15]);
1022 wt[1] = wtDummy;
1023 wt[2] = wtDummy;
1024 wt[3] = TRGState(5, timing[31]);
1025 wt[4] = wtDummy;
1026 wt[5] = wtDummy;
1027
1028 //...Append 6th bit to indicate hit or not (no hit = 1)...
1029 if (! hitptn[15]) wt[0].set(5, true);
1030 if (! hitptn[31]) wt[3].set(5, true);
1031 } else {
1032 wt[0] = TRGState(5, timing[i - 1]);
1033 wt[1] = TRGState(5, timing[i]);
1034 wt[2] = TRGState(5, timing[i + 1]);
1035 wt[3] = TRGState(5, timing[i + 15]);
1036 wt[4] = TRGState(5, timing[i + 16]);
1037 wt[5] = TRGState(5, timing[i + 32]);
1038
1039 //...Append 6th bit to indicate hit or not (no hit = 1)...
1040 if (! hitptn[i - 1]) wt[0].set(5, true);
1041 if (! hitptn[i]) wt[1].set(5, true);
1042 if (! hitptn[i + 1]) wt[2].set(5, true);
1043 if (! hitptn[i + 15]) wt[3].set(5, true);
1044 if (! hitptn[i + 16]) wt[4].set(5, true);
1045 if (! hitptn[i + 32]) wt[5].set(5, true);
1046 }
1047
1048 //...Look for the fastest hit...
1049 unsigned fastest0 = 0;
1050 unsigned fastest1 = 0;
1051 unsigned fastest2 = 0;
1052 if (wt[0] < wt[1])
1053 fastest0 = 0;
1054 else
1055 fastest0 = 1;
1056 if (wt[2] < wt[3])
1057 fastest1 = 2;
1058 else
1059 fastest1 = 3;
1060 if (wt[4] < wt[5])
1061 fastest2 = 4;
1062 else
1063 fastest2 = 5;
1064
1065 unsigned fastest3 = 0;
1066 if (wt[fastest0] < wt[fastest1])
1067 fastest3 = fastest0;
1068 else
1069 fastest3 = fastest1;
1070
1071 unsigned fastest4 = 0;
1072 if (wt[fastest2] < wt[fastest3])
1073 fastest4 = fastest2;
1074 else
1075 fastest4 = fastest3;
1076
1077 TRGState fastest(5);
1078 if (! wt[fastest4].active(5))
1079 fastest = wt[fastest4].subset(0, 5);
1080
1081 s.set(p, fastest);
1082 p += 5;
1083 }
1084
1085 //s.set(p, 5, timing[0]);
1086 //p += 5;
1087 //s.set(p, 5, timing[15]);
1088 //p += 5;
1089 //s.set(p, 5, timing[31]);
1090
1091#ifdef TRG_DEBUG
1092// unpackerOuterInside(input, s);
1093#endif
1094
1095 delete[] b;
1096 return s;
1097 }
1098
1099 TRGState
1100 TRGCDCFrontEnd::packerOuterOutside(const TRGState& input)
1101 {
1102
1103 //...Input should be 48 hit pattern and 48x5 timing, total 288 bits...
1104 //
1105 // Wire numbers and TS ID
1106 //
1107 // outside
1108 //
1109 // +--+--+--+--+- -+--+--+--+--+--+--+
1110 // | 47 | 46 | .... | 34 | 33 | 32 |
1111 // +--+--+--+--+--+- -+--+--+--+--+--+--+
1112 // | 31 | 30 | ..... | 18 | 17 | 16 |
1113 // +--+--+--+--+--+- -+--+--+--+--+--+--+
1114 // | 15 | 14 | .... | 2 | 1 | 0 | <- second priority wire layer
1115 // +--+--+--+--+- -+--+--+--+--+--+--+
1116 //
1117 // 15 14 .... 2 1 0 <- partial TS ID
1118 //
1119 // inside
1120 //
1121 //
1122
1123 //...Prepare a state for output...
1124 //TRGState s(48 + 16 * 5 + 16 * 5 + 3 * 5); // 3*5 for missing wires
1125 TRGState s(48 + 16 * 5 + 16 * 5 + 2 * 5 + 38); // 2*5 for edge fastest time, 38 dummy bits to fill to 256 bits
1126
1127
1128 //...Set up bool array...
1129 bool* b = new bool[input.size()];
1
Storing uninitialized value
→
1130 input.copy2bool(b);
2
←
Calling 'TRGState::copy2bool'
→
8
←
Returning from 'TRGState::copy2bool'
→
1131
1132 //...Naming...
1133 const bool* const hitptn = & b[0]; // 16x3 = 48 bits
1134 const bool* const timing[48] = {
1135 & b[48], & b[53], & b[58], & b[63],
1136 & b[68], & b[73], & b[78], & b[83],
1137 & b[88], & b[93], & b[98], & b[103],
1138 & b[108], & b[113], & b[118], & b[123],
1139 & b[128], & b[133], & b[138], & b[143],
1140 & b[148], & b[153], & b[158], & b[163],
1141 & b[168], & b[173], & b[178], & b[183],
1142 & b[188], & b[193], & b[198], & b[203],
1143 & b[208], & b[213], & b[218], & b[223],
1144 & b[228], & b[233], & b[238], & b[243],
1145 & b[248], & b[253], & b[258], & b[263],
1146 & b[268], & b[273], & b[278], & b[283]
1147 };
1148
1149 //...Store hit pattern...
1150 s.set(0, 48, hitptn);
9
←
Calling 'TRGState::set'
→
1151 unsigned p = 48;
1152
1153
1154 //...Second priority cell timing...
1155 for (unsigned i = 0; i < 16; i++) {
1156 s.set(p, 5, timing[i]);
1157 p += 5;
1158 }
1159
1160 //...Fastest timing...
1161 const bool dummy[6] = {false, false, false, false, false, true};
1162 const TRGState wtDummy(6, dummy);
1163 for (unsigned i = 0; i < 18; i++) { // 0 ... 15 for 16 standard ones, 16,17 for two edge areas.
1164 TRGState wt[5];
1165
1166 if (i == 0) { // TS ID 0 has missing wires
1167 wt[0] = wtDummy;
1168 wt[1] = TRGState(5, timing[0]);
1169 wt[2] = wtDummy;
1170 wt[3] = TRGState(5, timing[16]);
1171 wt[4] = TRGState(5, timing[17]);
1172
1173 //...Append 6th bit to indicate hit or not (no hit = 1)...
1174 if (! hitptn[0]) wt[1].set(5, true);
1175 if (! hitptn[16]) wt[3].set(5, true);
1176 if (! hitptn[17]) wt[4].set(5, true);
1177 } else if (i == 15) { // TS ID 15 has missing wires
1178 wt[0] = TRGState(5, timing[14]);
1179 wt[1] = TRGState(5, timing[15]);
1180 wt[2] = TRGState(5, timing[30]);
1181 wt[3] = TRGState(5, timing[31]);
1182 wt[4] = wtDummy;
1183
1184 //...Append 6th bit to indicate hit or not (no hit = 1)...
1185 if (! hitptn[14]) wt[0].set(5, true);
1186 if (! hitptn[15]) wt[1].set(5, true);
1187 if (! hitptn[30]) wt[2].set(5, true);
1188 if (! hitptn[31]) wt[3].set(5, true);
1189 } else if (i == 16) { // edge area 1 only for cell 16
1190 wt[0] = wtDummy;
1191 wt[1] = wtDummy;
1192 wt[2] = wtDummy;
1193 wt[3] = wtDummy;
1194 wt[4] = TRGState(5, timing[16]);
1195 //...Append 6th bit to indicate hit or not (no hit = 1)...
1196 if (! hitptn[16]) wt[4].set(5, true);
1197 } else if (i == 17) { // edge area 2 for cell 15 and 31 only
1198 wt[0] = TRGState(5, timing[15]);
1199 wt[1] = wtDummy;
1200 wt[2] = TRGState(5, timing[31]);
1201 wt[3] = wtDummy;
1202 wt[4] = wtDummy;
1203
1204 //...Append 6th bit to indicate hit or not (no hit = 1)...
1205 if (! hitptn[15]) wt[0].set(5, true);
1206 if (! hitptn[31]) wt[2].set(5, true);
1207 } else {
1208 wt[0] = TRGState(5, timing[i - 1]);
1209 wt[1] = TRGState(5, timing[i]);
1210 wt[2] = TRGState(5, timing[i + 15]);
1211 wt[3] = TRGState(5, timing[i + 16]);
1212 wt[4] = TRGState(5, timing[i + 17]);
1213
1214 //...Append 6th bit to indicate hit or not (no hit = 1)...
1215 if (! hitptn[i - 1]) wt[0].set(5, true);
1216 if (! hitptn[i]) wt[1].set(5, true);
1217 if (! hitptn[i + 15]) wt[2].set(5, true);
1218 if (! hitptn[i + 16]) wt[3].set(5, true);
1219 if (! hitptn[i + 17]) wt[4].set(5, true);
1220 }
1221
1222 //...Look for the fastest hit...
1223 unsigned fastest0 = 0;
1224 unsigned fastest1 = 0;
1225 if (wt[0] < wt[1])
1226 fastest0 = 0;
1227 else
1228 fastest0 = 1;
1229 if (wt[2] < wt[3])
1230 fastest1 = 2;
1231 else
1232 fastest1 = 3;
1233
1234 unsigned fastest2 = 0;
1235 if (wt[fastest0] < wt[fastest1])
1236 fastest2 = fastest0;
1237 else
1238 fastest2 = fastest1;
1239
1240 unsigned fastest3 = 0;
1241 if (wt[fastest2] < wt[4])
1242 fastest3 = fastest2;
1243 else
1244 fastest3 = 4;
1245
1246 TRGState fastest(5);
1247 if (! wt[fastest3].active(5))
1248 fastest = wt[fastest3].subset(0, 5);
1249
1250 s.set(p, fastest);
1251 p += 5;
1252 }
1253
1254 //s.set(p, 5, timing[16]);
1255 //p += 5;
1256 //s.set(p, 5, timing[15]);
1257 //p += 5;
1258 //s.set(p, 5, timing[31]);
1259
1260#ifdef TRG_DEBUG
1261// unpackerOuterOutside(input, s);
1262#endif
1263
1264 delete[] b;
1265 return s;
1266 }
1267
1268 void
1269 TRGCDCFrontEnd::unpackerInnerInside(const TRGState& input,
1270 const TRGState& output)
1271 {
1272
1273 cout << "Input bit size=" << input.size() << endl;
1274
1275 cout << "Input : wire hit pattern" << endl;
1276 cout << " ";
1277 for (unsigned i = 0; i < 48; i++) {
1278 const unsigned j = 48 - i - 1;
1279 if (i && ((i % 8) == 0))
1280 cout << "_";
1281 if (input[j])
1282 cout << "1";
1283 else
1284 cout << "0";
1285 }
1286 cout << endl;
1287 cout << "Input : wire hit timing" << endl;
1288 unsigned o = 48;
1289 for (unsigned i = 0; i < 48; i++) {
1290 TRGState s = input.subset(o + i * 5, 5);
1291 if ((i % 4) == 0)
1292 cout << " ";
1293 cout << i << ": " << s << " ";
1294 if ((i % 4) == 3)
1295 cout << endl;
1296 }
1297
1298 cout << "Output bit size=" << output.size() << endl;
1299
1300 cout << "Output : wire hit pattern" << endl;
1301 cout << " ";
1302 for (unsigned i = 0; i < 32; i++) {
1303 const unsigned j = 32 - i - 1;
1304 if (i && ((i % 8) == 0))
1305 cout << "_";
1306 if (output[j])
1307 cout << "1";
1308 else
1309 cout << "0";
1310 }
1311 cout << endl;
1312
1313 cout << "Output : priority cell timing" << endl;
1314 o = 32;
1315 for (unsigned i = 0; i < 16; i++) {
1316 TRGState s = output.subset(o + i * 5, 5);
1317 if ((i % 4) == 0)
1318 cout << " ";
1319 cout << i << ": " << s << " ";
1320 if ((i % 4) == 3)
1321 cout << endl;
1322 }
1323
1324 cout << "Output : second priority cell position" << endl;
1325 cout << " ";
1326 o = 112;
1327 for (unsigned i = 0; i < 16; i++) {
1328 TRGState s = output.subset(o + i, 1);
1329 if (i && ((i % 8) == 0))
1330 cout << "_";
1331 if (s.active())
1332 cout << "1";
1333 else
1334 cout << "0";
1335 }
1336 cout << endl;
1337
1338 cout << "Output : fastest timing" << endl;
1339 o = 128;
1340 for (unsigned i = 0; i < 16; i++) {
1341 TRGState s = output.subset(o + i * 5, 5);
1342 if ((i % 4) == 0)
1343 cout << " ";
1344 cout << i << ": " << s << " ";
1345 if ((i % 4) == 3)
1346 cout << endl;
1347 }
1348
1349 cout << "Output : timing of missing wires" << endl;
1350 o = 208;
1351 for (unsigned i = 0; i < 1; i++) {
1352 TRGState s = output.subset(o + i * 5, 5);
1353 if ((i % 4) == 0)
1354 cout << " ";
1355 cout << i << ": " << s << " ";
1356 if ((i % 4) == 3)
1357 cout << endl;
1358 }
1359
1360 cout << endl;
1361 }
1362
1363 void
1364 TRGCDCFrontEnd::unpackerInnerOutside(const TRGState& input,
1365 const TRGState& output)
1366 {
1367
1368 cout << "Input bit size=" << input.size() << endl;
1369
1370 cout << "Input : wire hit pattern" << endl;
1371 cout << " ";
1372 for (unsigned i = 0; i < 48; i++) {
1373 const unsigned j = 48 - i - 1;
1374 if (i && ((i % 8) == 0))
1375 cout << "_";
1376 if (input[j])
1377 cout << "1";
1378 else
1379 cout << "0";
1380 }
1381 cout << endl;
1382 cout << "Input : wire hit timing" << endl;
1383 unsigned o = 48;
1384 for (unsigned i = 0; i < 48; i++) {
1385 TRGState s = input.subset(o + i * 5, 5);
1386 if ((i % 4) == 0)
1387 cout << " ";
1388 cout << i << ": " << s << " ";
1389 if ((i % 4) == 3)
1390 cout << endl;
1391 }
1392
1393 cout << "Output bit size=" << output.size() << endl;
1394
1395 cout << "Output : wire hit pattern" << endl;
1396 cout << " ";
1397 for (unsigned i = 0; i < 48; i++) {
1398 const unsigned j = 48 - i - 1;
1399 if (i && ((i % 8) == 0))
1400 cout << "_";
1401 if (output[j])
1402 cout << "1";
1403 else
1404 cout << "0";
1405 }
1406 cout << endl;
1407
1408 cout << "Output : fastest timing" << endl;
1409 o = 48;
1410 for (unsigned i = 0; i < 16; i++) {
1411 TRGState s = output.subset(o + i * 5, 5);
1412 if ((i % 4) == 0)
1413 cout << " ";
1414 cout << i << ": " << s << " ";
1415 if ((i % 4) == 3)
1416 cout << endl;
1417 }
1418
1419 cout << "Output : timing of missing wires" << endl;
1420 o = 128;
1421 for (unsigned i = 0; i < 4; i++) {
1422 TRGState s = output.subset(o + i * 5, 5);
1423 if ((i % 4) == 0)
1424 cout << " ";
1425 cout << i << ": " << s << " ";
1426 if ((i % 4) == 3)
1427 cout << endl;
1428 }
1429
1430 cout << endl;
1431 }
1432
1433 void
1434 TRGCDCFrontEnd::unpackerOuterInside(const TRGState& input,
1435 const TRGState& output)
1436 {
1437
1438 cout << "Input bit size=" << input.size() << endl;
1439
1440 cout << "Input : wire hit pattern" << endl;
1441 cout << " ";
1442 for (unsigned i = 0; i < 48; i++) {
1443 const unsigned j = 48 - i - 1;
1444 if (i && ((i % 8) == 0))
1445 cout << "_";
1446 if (input[j])
1447 cout << "1";
1448 else
1449 cout << "0";
1450 }
1451 cout << endl;
1452 cout << "Input : wire hit timing" << endl;
1453 unsigned o = 48;
1454 for (unsigned i = 0; i < 48; i++) {
1455 TRGState s = input.subset(o + i * 5, 5);
1456 if ((i % 4) == 0)
1457 cout << " ";
1458 cout << i << ": " << s << " ";
1459 if ((i % 4) == 3)
1460 cout << endl;
1461 }
1462
1463 cout << "Output bit size=" << output.size() << endl;
1464
1465 cout << "Output : wire hit pattern" << endl;
1466 cout << " ";
1467 for (unsigned i = 0; i < 48; i++) {
1468 const unsigned j = 48 - i - 1;
1469 if (i && ((i % 8) == 0))
1470 cout << "_";
1471 if (output[j])
1472 cout << "1";
1473 else
1474 cout << "0";
1475 }
1476 cout << endl;
1477
1478 cout << "Output : priority cell timing" << endl;
1479 o = 48;
1480 for (unsigned i = 0; i < 16; i++) {
1481 TRGState s = output.subset(o + i * 5, 5);
1482 if ((i % 4) == 0)
1483 cout << " ";
1484 cout << i << ": " << s << " ";
1485 if ((i % 4) == 3)
1486 cout << endl;
1487 }
1488
1489 cout << "Output : fastest timing" << endl;
1490 o = 128;
1491 for (unsigned i = 0; i < 16; i++) {
1492 TRGState s = output.subset(o + i * 5, 5);
1493 if ((i % 4) == 0)
1494 cout << " ";
1495 cout << i << ": " << s << " ";
1496 if ((i % 4) == 3)
1497 cout << endl;
1498 }
1499
1500 cout << "Output : timing of missing wires" << endl;
1501 o = 208;
1502 for (unsigned i = 0; i < 2; i++) {
1503 TRGState s = output.subset(o + i * 5, 5);
1504 if ((i % 4) == 0)
1505 cout << " ";
1506 cout << i << ": " << s << " ";
1507 if ((i % 4) == 3)
1508 cout << endl;
1509 }
1510
1511 cout << endl;
1512 }
1513
1514 void
1515 TRGCDCFrontEnd::unpackerOuterOutside(const TRGState& input,
1516 const TRGState& output)
1517 {
1518
1519 cout << "Input bit size=" << input.size() << endl;
1520
1521 cout << "Input : wire hit pattern" << endl;
1522 cout << " ";
1523 for (unsigned i = 0; i < 48; i++) {
1524 const unsigned j = 48 - i - 1;
1525 if (i && ((i % 8) == 0))
1526 cout << "_";
1527 if (input[j])
1528 cout << "1";
1529 else
1530 cout << "0";
1531 }
1532 cout << endl;
1533 cout << "Input : wire hit timing" << endl;
1534 unsigned o = 48;
1535 for (unsigned i = 0; i < 48; i++) {
1536 TRGState s = input.subset(o + i * 5, 5);
1537 if ((i % 4) == 0)
1538 cout << " ";
1539 cout << i << ": " << s << " ";
1540 if ((i % 4) == 3)
1541 cout << endl;
1542 }
1543
1544 cout << "Output bit size=" << output.size() << endl;
1545
1546 cout << "Output : wire hit pattern" << endl;
1547 cout << " ";
1548 for (unsigned i = 0; i < 48; i++) {
1549 const unsigned j = 48 - i - 1;
1550 if (i && ((i % 8) == 0))
1551 cout << "_";
1552 if (output[j])
1553 cout << "1";
1554 else
1555 cout << "0";
1556 }
1557 cout << endl;
1558
1559 cout << "Output : Second priority cell timing" << endl;
1560 o = 48;
1561 for (unsigned i = 0; i < 16; i++) {
1562 TRGState s = output.subset(o + i * 5, 5);
1563 if ((i % 4) == 0)
1564 cout << " ";
1565 cout << i << ": " << s << " ";
1566 if ((i % 4) == 3)
1567 cout << endl;
1568 }
1569
1570 cout << "Output : fastest timing" << endl;
1571 o = 128;
1572 for (unsigned i = 0; i < 16; i++) {
1573 TRGState s = output.subset(o + i * 5, 5);
1574 if ((i % 4) == 0)
1575 cout << " ";
1576 cout << i << ": " << s << " ";
1577 if ((i % 4) == 3)
1578 cout << endl;
1579 }
1580
1581 cout << "Output : timing of missing wires" << endl;
1582 o = 208;
1583 for (unsigned i = 0; i < 2; i++) {
1584 TRGState s = output.subset(o + i * 5, 5);
1585 if ((i % 4) == 0)
1586 cout << " ";
1587 cout << i << ": " << s << " ";
1588 if ((i % 4) == 3)
1589 cout << endl;
1590 }
1591 cout << endl;
1592 }
1593
1594
1595 void //Dump all the details of _mosb into a .log file, do it in the end of simulate()
1596 TRGCDCFrontEnd::dump_log(void) const
1597 {
1598
1599 if (type() == innerInside) dump_log_innerInside();
1600 else if (type() == innerOutside) dump_log_innerOutside();
1601 else if (type() == outerInside) dump_log_outerInside();
1602 else if (type() == outerOutside) dump_log_outerOutside();
1603
1604 }
1605
1606 void
1607 TRGCDCFrontEnd::dump_log_innerInside(void) const
1608 {
1609
1610 const TRGClock& dClock = TRGCDC::getTRGCDC()->dataClock();
1611 ofstream output((name() + ".log").c_str());
1612
1613 output << "InnerInside FrontEnd output dump" << endl << endl;
1614
1615 const std::vector<int> changetime = _osb->stateChanges();
1616 std::vector<vector<int>> boolvector(changetime.size());
1617 for (unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1618
1619 for (unsigned b = 0; b < (* _osb)[0]->size(); b++) {
1620 boolvector[ch_t].push_back(((* _osb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1621 }
1622
1623 output << "# of clk: " << changetime[ch_t] << " (" << dClock.absoluteTime(changetime[ch_t]) << " ns), signal vector: " << endl;
1624
1625 output << "Hitmap: " << endl ;
1626 for (unsigned b = 0; b < 32; b++) {
1627 output << boolvector[ch_t][31 - b] << " " ;
1628 if (b == 15) output << endl << " ";
1629 }
1630 output << endl;
1631
1632 for (unsigned b = 0; b < 16; b++) {
1633 output << "PT#" << b << ": " << boolvector[ch_t][ 32 + 5 * b + 4 ] << boolvector[ch_t][ 32 + 5 * b + 3 ] << boolvector[ch_t][ 32 + 5
1634 * b + 2 ]
1635 << boolvector[ch_t][ 32 + 5 * b + 1 ] << boolvector[ch_t][ 32 + 5 * b] << endl;
1636 }
1637 output << endl;
1638
1639 output << "Secondary: ";
1640 for (int b = 0; b < 16; b++) {
1641 output << boolvector[ch_t][ 127 - b ] ;
1642 }
1643 output << endl;
1644
1645 for (unsigned b = 0; b < 16; b++) {
1646 output << "FT#" << b << ": " << boolvector[ch_t][ 128 + 5 * b + 4 ] << boolvector[ch_t][ 128 + 5 * b + 3 ] << boolvector[ch_t][ 128
1647 + 5 * b + 2 ]
1648 << boolvector[ch_t][ 128 + 5 * b + 1 ] << boolvector[ch_t][ 128 + 5 * b] << endl;
1649 }
1650
1651 output << endl;
1652 output << "ET#0(cell 31): " << endl << boolvector[ch_t][212] << boolvector[ch_t][211] << boolvector[ch_t][210]
1653 << boolvector[ch_t][209] << boolvector[ch_t][208] << endl;
1654
1655 output << endl;
1656 }
1657
1658 output.close();
1659
1660 }
1661
1662
1663 void
1664 TRGCDCFrontEnd::dump_log_innerOutside(void) const
1665 {
1666
1667 const TRGClock& dClock = TRGCDC::getTRGCDC()->dataClock();
1668 ofstream output((name() + ".log").c_str());
1669
1670 output << "InnerOutside FrontEnd output dump" << endl << endl;
1671
1672 const std::vector<int> changetime = _osb->stateChanges();
1673 std::vector<vector<int>> boolvector(changetime.size());
1674 for (unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1675
1676 for (unsigned b = 0; b < (* _osb)[0]->size(); b++) {
1677 boolvector[ch_t].push_back(((* _osb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1678 }
1679
1680 output << "# of clk: " << changetime[ch_t] << " (" << dClock.absoluteTime(changetime[ch_t]) << " ns), signal vector: " << endl;
1681
1682 output << "Hitmap: " << endl << " ";
1683 for (unsigned b = 0; b < 48; b++) {
1684 output << boolvector[ch_t][47 - b] << " ";
1685 if (b == 15) output << endl ;
1686 else if (b == 31) output << endl << " ";
1687 }
1688 output << endl;
1689
1690 for (unsigned b = 0; b < 16; b++) {
1691 output << "FT#" << b << ": " << boolvector[ch_t][ 48 + 5 * b + 4 ] << boolvector[ch_t][ 48 + 5 * b + 3 ] << boolvector[ch_t][ 48 + 5
1692 * b + 2 ]
1693 << boolvector[ch_t][ 48 + 5 * b + 1 ] << boolvector[ch_t][ 48 + 5 * b] << endl;
1694 }
1695
1696 output << endl;
1697 output << "ET#0(cell 32): " << endl << boolvector[ch_t][132] << boolvector[ch_t][131] << boolvector[ch_t][130]
1698 << boolvector[ch_t][129] << boolvector[ch_t][128] << endl;
1699 output << "ET#1(cell 0, 16, 32, 33): " << endl << boolvector[ch_t][137] << boolvector[ch_t][136] << boolvector[ch_t][135]
1700 << boolvector[ch_t][134] << boolvector[ch_t][133] << endl;
1701 output << "ET#0(cell 15, 30, 31, 46, 47): " << endl << boolvector[ch_t][142] << boolvector[ch_t][141] << boolvector[ch_t][140]
1702 << boolvector[ch_t][139] << boolvector[ch_t][138] << endl;
1703 output << "ET#3(cell 31, 47): " << endl << boolvector[ch_t][147] << boolvector[ch_t][146] << boolvector[ch_t][145]
1704 << boolvector[ch_t][144] << boolvector[ch_t][143] << endl;
1705
1706 output << endl;
1707 }
1708
1709 output.close();
1710 }
1711
1712
1713 void
1714 TRGCDCFrontEnd::dump_log_outerInside(void) const
1715 {
1716
1717 const TRGClock& dClock = TRGCDC::getTRGCDC()->dataClock();
1718 ofstream output((name() + ".log").c_str());
1719
1720 output << "OuterInside FrontEnd output dump" << endl << endl;
1721
1722 const std::vector<int> changetime = _osb->stateChanges();
1723 std::vector<vector<int>> boolvector(changetime.size());
1724 for (unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1725
1726 for (unsigned b = 0; b < (* _osb)[0]->size(); b++) {
1727 boolvector[ch_t].push_back(((* _osb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1728 }
1729
1730 output << "# of clk: " << changetime[ch_t] << " (" << dClock.absoluteTime(changetime[ch_t]) << " ns), signal vector: " << endl;
1731
1732 output << "Hitmap: " << endl << " ";
1733 for (unsigned b = 0; b < 48; b++) {
1734 output << boolvector[ch_t][47 - b] << " " ;
1735 if (b == 15) output << endl;
1736 else if (b == 31) output << endl << " ";
1737 }
1738 output << endl;
1739
1740 for (unsigned b = 0; b < 16; b++) {
1741 output << "PT#" << b << ": " << boolvector[ch_t][ 48 + 5 * b + 4 ] << boolvector[ch_t][ 48 + 5 * b + 3 ] << boolvector[ch_t][ 48 + 5
1742 * b + 2 ]
1743 << boolvector[ch_t][ 48 + 5 * b + 1 ] << boolvector[ch_t][ 48 + 5 * b] << endl;
1744 }
1745 output << endl;
1746
1747 for (unsigned b = 0; b < 16; b++) {
1748 output << "FT#" << b << ": " << boolvector[ch_t][ 128 + 5 * b + 4 ] << boolvector[ch_t][ 128 + 5 * b + 3 ] << boolvector[ch_t][ 128
1749 + 5 * b + 2 ]
1750 << boolvector[ch_t][ 128 + 5 * b + 1 ] << boolvector[ch_t][ 128 + 5 * b] << endl;
1751 }
1752
1753 output << endl;
1754 output << "ET#0(cell 0): " << endl << boolvector[ch_t][212] << boolvector[ch_t][211] << boolvector[ch_t][210]
1755 << boolvector[ch_t][209] << boolvector[ch_t][208] << endl;
1756 output << "ET#1(cell 15, 31): " << endl << boolvector[ch_t][217] << boolvector[ch_t][216] << boolvector[ch_t][215]
1757 << boolvector[ch_t][214] << boolvector[ch_t][213] << endl;
1758
1759 output << endl;
1760 }
1761
1762 output.close();
1763
1764 }
1765
1766 void
1767 TRGCDCFrontEnd::dump_log_outerOutside(void) const
1768 {
1769
1770 const TRGClock& dClock = TRGCDC::getTRGCDC()->dataClock();
1771 ofstream output((name() + ".log").c_str());
1772
1773 output << "OuterOutside FrontEnd output dump" << endl << endl;
1774 const std::vector<int> changetime = _osb->stateChanges();
1775 std::vector<vector<int>> boolvector(changetime.size());
1776 for (unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1777
1778 for (unsigned b = 0; b < (* _osb)[0]->size(); b++) {
1779 boolvector[ch_t].push_back(((* _osb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1780 }
1781
1782 output << "# of clk: " << changetime[ch_t] << " (" << dClock.absoluteTime(changetime[ch_t]) << " ns), signal vector: " << endl;
1783
1784 output << "Hitmap: " << endl;
1785 for (unsigned b = 0; b < 48; b++) {
1786 output << boolvector[ch_t][47 - b] << " ";
1787 if (b == 15) output << endl << " ";
1788 else if (b == 31) output << endl ;
1789 }
1790 output << endl;
1791
1792 for (unsigned b = 0; b < 16; b++) {
1793 output << "PT#" << b << ": " << boolvector[ch_t][ 48 + 5 * b + 4 ] << boolvector[ch_t][ 48 + 5 * b + 3 ] << boolvector[ch_t][ 48 + 5
1794 * b + 2 ]
1795 << boolvector[ch_t][ 48 + 5 * b + 1 ] << boolvector[ch_t][ 48 + 5 * b] << endl;
1796 }
1797 output << endl;
1798
1799 for (unsigned b = 0; b < 16; b++) {
1800 output << "FT#" << b << ": " << boolvector[ch_t][ 128 + 5 * b + 4 ] << boolvector[ch_t][ 128 + 5 * b + 3 ] << boolvector[ch_t][ 128
1801 + 5 * b + 2 ]
1802 << boolvector[ch_t][ 128 + 5 * b + 1 ] << boolvector[ch_t][ 128 + 5 * b] << endl;
1803 }
1804
1805 output << endl;
1806 output << "ET#0(cell 16): " << endl << boolvector[ch_t][212] << boolvector[ch_t][211] << boolvector[ch_t][210]
1807 << boolvector[ch_t][209] << boolvector[ch_t][208] << endl;
1808 output << "ET#1(cell 15, 31): " << endl << boolvector[ch_t][217] << boolvector[ch_t][216] << boolvector[ch_t][215]
1809 << boolvector[ch_t][214] << boolvector[ch_t][213] << endl;
1810
1811
1812 output << endl;
1813 }
1814
1815
1816 output.close();
1817 }
1818
1819
1820
1821} // namespace Belle2
←

include/trg/trg/State.h

1/**************************************************************************
2 * basf2 (Belle II Analysis Software Framework) *
3 * Author: The Belle II Collaboration *
4 * *
5 * See git log for contributors and copyright holders. *
6 * This file is licensed under LGPL-3.0, see LICENSE.md. *
7 **************************************************************************/
8
9#ifndef TRGState_FLAG_
10#define TRGState_FLAG_
11
12#include <vector>
13#include <iomanip>
14#include <iostream>
15#include <sstream>
16
17namespace Belle2 {
18
19/// A class to represent a state of multi bits
20 class TRGState {
21
22 public:
23
24 /// Default constructor.
25 TRGState(unsigned bitSize = 0);
26
27 /// Constructor with unsigned.
28 TRGState(unsigned bitSize, unsigned value);
29
30 /// Constructor.
31 // cppcheck-suppress noExplicitConstructor
32 TRGState(std::vector<bool> states);
33
34 /// Constructor.
35 TRGState(unsigned bitSize, const bool* const states);
36
37 /// Constructor. order: 0=>inVector[0] is lsb. 1=>inVector[0] is msb.
38 TRGState(std::vector<unsigned>& states, unsigned order);
39
40 /// Constructor. type: 0-> binary, 1->hex
41 TRGState(const char*, unsigned type);
42
43 /// Default copy constructor.
44 TRGState(const TRGState&) = default;
45
46 /// Destructor
47 virtual ~TRGState();
48
49 public:// Selectors
50
51 /// returns bit size.
52 unsigned size(void) const;
53
54 /// returns true if there are active bits.
55 bool active(void) const;
56
57 /// returns true if there are active bits.
58 bool active(unsigned bitPosition) const;
59
60 /// returns a filled array.
61 void copy2bool(bool* array) const;
62
63 /// returns subset from i with n bits.
64 TRGState subset(unsigned i, unsigned n) const;
65
66 /// dumps contents. "message" is to select information to
67 /// dump. "pre" will be printed in head of each line.
68 void dump(const std::string& message = "",
69 const std::string& pre = "") const;
70
71 public:// Modifiers
72
73 /// clears state.
74 void clear(void);
75
76 /// sets state at bit i.
77 const TRGState& set(unsigned position, bool state = true);
78
79 /// sets state.
80 const TRGState& set(unsigned position,
81 unsigned size,
82 const bool* const array);
83
84 /// sets state.
85 const TRGState& set(unsigned position,
86 unsigned size,
87 unsigned value);
88
89 /// sets state.
90 const TRGState& set(unsigned position, const TRGState&);
91
92 public:// Operators
93
94 /// Conversion to unsigned.
95 operator unsigned() const;
96
97 /// Conversion to unsigned long long
98 operator unsigned long long() const;
99
100 /// Conversion to string
101 operator std::string() const;
102
103 /// appends TRGState (as MSB).
104 TRGState& operator+=(const TRGState&);
105
106 /// returns state of i'th bit.
107 bool operator[](unsigned i) const;
108
109 /// Copy operator.
110 TRGState& operator=(const TRGState&);
111
112 /// Copy operator.
113 bool operator<(const TRGState&) const;
114
115 /// shifts bits.
116 TRGState& shift(unsigned i);
117
118 public:// Utilities
119
120 /// Converts from bool array to unsigned.
121 static unsigned toUnsigned(unsigned n, const bool* array);
122
123 private:
124
125 /// size of unsigned.
126 static const unsigned _su;
127
128 /// bit size of unsigned.
129 static const unsigned _bsu;
130
131 /// bit size.
132 unsigned _size;
133
134 /// bit storage size.
135 unsigned _n;
136
137 /// bit state.
138 unsigned* _state;
139 };
140
141//-----------------------------------------------------------------------------
142
143 inline
144 unsigned
145 TRGState::size(void) const
146 {
147 return _size;
148 }
149
150 inline
151 bool
152 TRGState::active(void) const
153 {
154 for (unsigned i = 0; i < _n; i++)
155 if (_state[i])
156 return true;
157 return false;
158 }
159
160 inline
161 bool
162 TRGState::active(unsigned a) const
163 {
164 const unsigned wp = a / _bsu;
165 const unsigned bp = a % _bsu;
166 if (_state[wp] & (1 << bp))
167 return true;
168 else
169 return false;
170 }
171
172 inline
173 bool
174 TRGState::operator[](unsigned a) const
175 {
176#ifdef TRG_DEBUG
177 if (a >= _size)
178 std::cout << "TRGState::operator[] !!! bit size overflow"
179 << ":bit size=" << _size << ",specified position=" << a
180 << std::endl;
181#endif
182
183 const unsigned wp = a / _bsu;
184 const unsigned bp = a % _bsu;
185 if (_state[wp] & (1 << bp))
186 return true;
187 else
188 return false;
189 }
190
191 inline
192 TRGState::operator unsigned() const
193 {
194#ifdef TRG_DEBUG
195 unsigned n = _size / _bsu;
196 if (_size % _bsu) ++n;
197 if (n > 1)
198 std::cout << "TRGState::operator unsigned() !!! bit size overflow"
199 << ":bit size=" << _size << ",max bit size with unsigned="
200 << _bsu << std::endl;
201#endif
202 return _state[0];
203
204 }
205
206 inline
207 TRGState::operator unsigned long long() const
208 {
209 unsigned n = _size / _bsu;
210 if (_size % _bsu) ++n;
211 const unsigned c = sizeof(unsigned long long);
212 if (n > c)
213#ifdef TRG_DEBUG
214 std::cout << "TRGState::operator unsigned long long() "
215 << "!!! bit size overflow"
216 << ":bit size=" << _size
217 << ",max bit size with unsigned long long="
218 << c << std::endl;
219#endif
220 n = c;
221 unsigned long long a = 0;
222 const unsigned s = _bsu;
223 for (unsigned i = 0; i < n; i++) {
224 const unsigned long long b = _state[i];
225 a += b << (i * s);
226 }
227 return a;
228 }
229
230 inline
231 TRGState::operator std::string() const
232 {
233 unsigned nWords = _size / _bsu;
234 if (_size % _bsu) ++nWords;
235 unsigned lastNHex = (_size % _bsu);
236 if (lastNHex == 0) lastNHex = 8;
237 else {
238 lastNHex = lastNHex / 4;
239 if ((_size % _bsu) % 4) ++lastNHex;
240 }
241 std::stringstream t_stringstream;
242 t_stringstream << std::setw(lastNHex) << std::setfill('0') << std::hex << _state[nWords - 1];
243 for (unsigned iWord = 1; iWord < nWords; iWord++) {
244 t_stringstream << std::setw(8) << std::setfill('0') << std::hex << _state[nWords - 1 - iWord];
245 }
246 return t_stringstream.str();
247 }
248
249 inline
250 void
251 TRGState::copy2bool(bool* a) const
252 {
253 for (unsigned i = 0; i
2.1
'i' is < field '_size'
2.1
'i' is < field '_size'
 < _size; i++) {
3
←
Loop condition is true. Entering loop body
→
6
←
Assuming 'i' is >= field '_size'
→
7
←
Loop condition is false. Execution continues on line 1130
→
254 const unsigned wp = i / _bsu;
255 const unsigned bp = i % _bsu;
256 if (_state[wp] & (1 << bp))
4
←
Assuming the condition is false
→
5
←
Taking false branch
→
257 a[i] = true;
258 else
259 a[i] = false;
260 }
261 }
262
263 inline
264 const TRGState&
265 TRGState::set(unsigned p, unsigned n, const bool* const a)
266 {
267 if (a
9.1
'a' is non-null
9.1
'a' is non-null
) {
10
←
Taking true branch
→
268 for (unsigned i = 0; i < n; i++) {
11
←
Loop condition is true. Entering loop body
→
13
←
The value 1 is assigned to 'i'
→
14
←
Loop condition is true. Entering loop body
→
269 const unsigned wp = (p + i) / _bsu;
270 const unsigned bp = (p + i) % _bsu;
271 if (a[i])
12
←
Taking false branch
→
15
←
Branch condition evaluates to a garbage value
272 _state[wp] |= (1 << bp);
273 else
274 _state[wp] &= ~(1 << bp);
275 }
276 }
277#ifdef TRG_DEBUG
278 else std::cout << "NULL pointer found in TRGState::set"
279 << std::endl;
280#endif
281 return * this;
282 }
283
284 inline
285 const TRGState&
286 TRGState::set(unsigned p, unsigned n, unsigned a)
287 {
288 for (unsigned i = 0; i < n; i++) {
289 const unsigned wp = (p + i) / _bsu;
290 const unsigned bp = (p + i) % _bsu;
291 if (a & (1 << i))
292 _state[wp] |= (1 << bp);
293 else
294 _state[wp] &= ~(1 << bp);
295 }
296 return * this;
297 }
298
299 inline
300 const TRGState&
301 TRGState::set(unsigned n, bool a)
302 {
303 const unsigned wp = n / _bsu;
304 const unsigned bp = n % _bsu;
305 if (a)
306 _state[wp] |= (1 << bp);
307 else
308 _state[wp] &= ~(1 << bp);
309 return * this;
310 }
311
312 inline
313 const TRGState&
314 TRGState::set(unsigned p, const TRGState& s)
315 {
316 const unsigned n = s.size();
317 for (unsigned i = 0; i < n; i++) {
318 const unsigned wp = (p + i) / _bsu;
319 const unsigned bp = (p + i) % _bsu;
320 if (s[i])
321 _state[wp] |= (1 << bp);
322 else
323 _state[wp] &= ~(1 << bp);
324 }
325 return * this;
326 }
327
328 inline
329 unsigned
330 TRGState::toUnsigned(unsigned n, const bool* a)
331 {
332#ifdef TRG_DEBUG
333 if (n > 8) std::cout << "given array size(" << n << ") is too big"
334 << std::endl;
335#endif
336
337 unsigned b = 0;
338 for (unsigned i = 0; i < n; i++) {
339 if (a[i]) {
340 const unsigned bp = i % _bsu;
341 b |= (1 << bp);
342 }
343 }
344 return b;
345 }
346
347 inline
348 TRGState&
349 TRGState::shift(unsigned a)
350 {
351
352 if (! active()) return * this;
353
354 if (a == 0) return * this;
355
356 for (int i = _size - 1; i >= 0; --i) {
357 if (i < int(a))
358 set(i, false);
359 else
360 set(i, active(i - a));
361 }
362
363 return * this;
364 }
365
366 inline
367 void
368 TRGState::clear(void)
369 {
370 for (unsigned i = 0; i < _n; i++)
371 _state[i] = 0;
372 }
373
374} // namespace Belle2
375
376//-----------------------------------------------------------------------------
377
378namespace std {
379
380 ostream& operator<<(ostream&, const Belle2::TRGState&);
381
382}
383
384#endif /* TRGState_FLAG_ */