Belle II Software development
SignalBundle.cc
1/**************************************************************************
2 * basf2 (Belle II Analysis Software Framework) *
3 * Author: The Belle II Collaboration *
4 * *
5 * See git log for contributors and copyright holders. *
6 * This file is licensed under LGPL-3.0, see LICENSE.md. *
7 **************************************************************************/
8
9#define TRG_SHORT_NAMES
10
11#include <string>
12#include <algorithm>
13#include <limits>
14#include <iostream>
15#include <fstream>
16#include "trg/trg/Utilities.h"
17#include "trg/trg/Debug.h"
18#include "trg/trg/Clock.h"
19#include "trg/trg/Signal.h"
20#include "trg/trg/SignalVector.h"
21#include "trg/trg/SignalBundle.h"
22#include "trg/trg/State.h"
23
24using namespace std;
25
26namespace Belle2 {
33 : _name("unknown"),
34 _clock(& c)
35 {
36 }
37
38 TRGSignalBundle::TRGSignalBundle(const string& name, const TRGClock& c)
39 : _name(name),
40 _clock(& c)
41 {
42 }
43
45 const TRGClock& c,
46 const TRGSignalBundle& input,
47 const unsigned outputBitSize,
48 TRGState(* packer)(const TRGState&))
49 : _name(name),
50 _clock(& c)
51 {
52
53 //...Get state information...
54 const vector<int> states = input.stateChanges();
55 const unsigned nStates = states.size();
56
57 //...Loop over all states...
58 vector<TRGState*> outputStates;
59 for (unsigned i = 0; i < nStates; i++) {
60 TRGState s = input.state(states[i]);
61
62 // if (TRGDebug::level()) {
63 // cout << TRGDebug::tab() << "Clock=" << states[i] << endl;
64 // }
65
66 outputStates.push_back(new TRGState((* packer)(s)));
67 }
68
69 //...Bit size of output...
70 // unsigned outputSize = 0;
71 // if (outputStates.size())
72 // outputSize = outputStates.back()->size();
73
74 //...Creat a SignalVector...
75 TRGSignalVector* sb = new TRGSignalVector(_name, c, outputBitSize);
76
77 //...Make a SignalVector...
78 // const TRGState &os0 = * outputStates[0];
79 // sb->set(os0, 0); delete &os0;
80 // const unsigned n = outputStates.size(); // same as nStates
81
82 for (unsigned i = 0; i < nStates; i++) {
83 const TRGState* s = outputStates[i];
84 sb->set((*s), states[i]);
85 delete s;
86 }
87
88 push_back(sb);
89 }
90
92 const TRGClock& clock,
93 const TRGSignalBundle& input,
94 const unsigned outputBitSize,
95 const unsigned registerBitSize,
96 TRGState(* packer)(const TRGState& in,
97 TRGState& registers,
98 bool& logicStillActive))
99 : _name(name),
100 _clock(& clock)
101 {
102
103 const string sn = "TRGSignalBundle constructor(4)";
105
106 //...Get state information...
107 const vector<int> states = input.stateChanges();
108 const unsigned nStates = states.size();
109
110 if (TRGDebug::level()) {
111 cout << TRGDebug::tab() << "#states=" << nStates << endl;
112 for (unsigned i = 0; i < nStates; i++)
113 cout << TRGDebug::tab() << i << " : " << states[i] << endl;
114 }
115
116 //...Input is stably inactive...
117 if (nStates == 0) {
118 TRGSignalVector* sb = new TRGSignalVector(_name, clock, outputBitSize);
119 push_back(sb);
121 return;
122 }
123
124 //...Loop over all states...
125 vector<TRGState*> outputStates;
126 vector<int> newStates;
127 int lastClock = states[0] - 1;
128 TRGState* r = new TRGState(registerBitSize);
129 for (unsigned i = 0; i < nStates; i++) {
130
131 if (TRGDebug::level())
132 cout << TRGDebug::tab() << "Last clock=" << lastClock << endl;
133
134 //...Check clock position...
135 if (states[i] <= lastClock)
136 continue;
137
138 if (TRGDebug::level()) {
139 cout << TRGDebug::tab() << "state=" << i << endl;
140 r->dump("", TRGDebug::tab() + "reg=");
141 }
142
143 bool active = true;
144 int nLoops = 0;
145 while (active) {
146 int clk = states[i] + nLoops;
147 lastClock = clk;
148
149 TRGState s = input.state(clk);
150 outputStates.push_back(new TRGState((* packer)(s, * r, active)));
151 newStates.push_back(clk);
152 ++nLoops;
153
154 if (TRGDebug::level()) {
155 cout << TRGDebug::tab() << "state=" << i << ",clock=" << clk <<
156 ",LogicActive=" << active << endl;
157 r->dump("", TRGDebug::tab() + "reg=");
158 }
159 }
160 }
161 delete r;
162
163 //...Size of output...
164 // unsigned outputSize = 0;
165 // if (outputStates.size())
166 // outputSize = outputStates.back()->size();
167
168 //...Creat a SignalVector...
169 TRGSignalVector* sb = new TRGSignalVector(_name, clock, outputBitSize);
170
171 //...Make a SignalVector...
172 // const TRGState &os0 = * outputStates[0];
173 // sb->set(os0, 0); delete &os0;
174 // const unsigned n = outputStates.size(); // same as nStates
175
176 const unsigned n = outputStates.size();
177 for (unsigned i = 0; i < n; i++) {
178 const TRGState* s = outputStates[i];
179 sb->set((* s), newStates[i]);
180 delete s;
181 }
182
183 push_back(sb);
184
186 }
187
189 {
190 }
191
192 void
193 TRGSignalBundle::dump(const string& msg,
194 const string& pre) const
195 {
196 cout << pre << _name << ":" << size() << " signal vector(s)" << endl;
197 for (unsigned i = 0; i < size(); i++)
198 (* this)[i]->dump(msg, " " + pre);
199 }
200
201 bool
203 {
204 for (unsigned i = 0; i < size(); i++)
205 if ((* this)[i]->active())
206 return true;
207 return false;
208 }
209
210 std::vector<int>
212 {
213
214 //...List for clock positions...
215 std::vector<int> list;
216
217 //...Pick up all clock points with state changes...
218 const unsigned n = size();
219 for (unsigned i = 0; i < n; i++) {
220 vector<int> a = (* this)[i]->stateChanges();
221 for (unsigned j = 0; j < a.size(); j++)
222 list.push_back(a[j]);
223 }
224
225 //...Append the first clock point if there are state changes...
226 if (list.size())
227 list.push_back(_clock->min());
228
229 //...Sorting...
230 std::sort(list.begin(), list.end());
231
232 //...Remove duplicated clock...
233 std::vector<int> list2;
234 int last = numeric_limits<int>::min();
235 for (unsigned i = 0; i < list.size(); i++) {
236 const int j = list[i];
237 if (j != last) {
238 list2.push_back(j);
239 last = j;
240 }
241 }
242 return list2;
243 }
244
246 TRGSignalBundle::state(int clockPosition) const
247 {
248 TRGState s;
249 const unsigned n = size();
250 for (unsigned i = 0; i < n; i++) {
251 TRGState t = (* this)[i]->state(clockPosition);
252 s += t;
253 }
254 return s;
255 }
256
257 const TRGClock&
259 {
260 _clock = & c;
261
262 for (unsigned i = 0; i < size(); i++) {
263 TRGSignalVector& t = * (* this)[i];
264 t.clock(c);
265 }
266
267 return * _clock;
268 }
269
272 {
273
274 //...Get state information...
275 const vector<int> states = stateChanges();
276 const unsigned nStates = states.size();
277
278 //...Output...
280
281 //...Loop over all states...
282 // vector<TRGState *> outputStates;
283 for (unsigned i = 0; i < nStates; i++) {
284 // if (TRGDebug::level())
285 // cout << TRGDebug::tab() << "Clock=" << states[i] << endl;
286
287 // if (active(states[i])) {
288 // TRGSignal p(* _clock,
289
290 // }
291
292
293 cout << "TRGSginalBundle::ored !!! not completed yet" << endl;
294 }
295
296 return TRGSignal();
297 }
298
299 void
300 TRGSignalBundle::dumpCOE(const string& fnIn, int start, int stop) const
301 {
302
303 string fn = fnIn;
304
305 if (fnIn.size() == 0)
306 fn = name();
307
308 //...Open a file to output...
309 ofstream file(fn + ".coe", ios::out);
310 if (! file.is_open()) {
311 cout << "!!! " << name() << " can not open file : " << fn << endl;
312 return;
313 }
314
315 // //...Determine start clock to output...
316 // int clk0 = _clock->max();
317 // vector<int> sc = stateChanges();
318 // for (unsigned i = 0; i < sc.size(); i++) {
319 // if (state(sc[i]).active()) {
320 // clk0 = sc[i];
321 // break;
322 // }
323 // }
324
325 // //...Determine end clock to output...
326 // int clk1 = _clock->min();
327 // for (unsigned i = 0; i < sc.size(); i++) {
328 // if (sc[i] < clk0)
329 // continue;
330
331 // if (state(sc[i]).active()) {
332 // clk1 = sc[i];
333 // }
334 // }
335
336 // //...No active case...
337 // if (clk0 > clk1) {
338 // clk0 = 0;
339 // clk1 = 1;
340 // }
341
342 // if (TRGDebug::level()) {
343 // cout << TRGDebug::tab() << "SignalBundle::dumpCOE : " << name()
344 // << endl;
345 // cout << TRGDebug::tab() << " clock region to output" << endl;
346 // cout << TRGDebug::tab() << " start=" << clk0 << endl;
347 // cout << TRGDebug::tab() << " end =" << clk1 << endl;
348 // }
349
350 // //...32 clocks as default : 2016/04...
351 // clk0 = 0;
352 // clk1 = 31;
353
354 int clk0 = start;
355 int clk1 = stop;
356
357 TRGState tmp = state(0);
358 const TRGSignalVector& cc = _clock->clockCounter();
359
360 file << "; " << name() << endl;
361 file << "; generated at " << TRGUtil::dateString() << endl;
362 file << "; start clock = " << clk0 << endl;
363 file << "; end clock = " << clk1 << endl;
364 file << "; bit size = " << tmp.size() << " + clock counter(" << cc.size()
365 << ")" << endl;
366 file << ";" << endl;
367 file << "memory_initialization_radix=2;" << endl;
368 file << "memory_initialization_vector=" << endl;
369
370 for (int i = clk0; i <= clk1; i++) {
371 TRGState sd = state(i);
372 TRGState sc = cc.state(i);
373 file << sc;
374 file << sd;
375 if (i == clk1)
376 file << ";" << endl;
377 else
378 file << "," << endl;
379 }
380
381 file.close();
382
383 }
384
386} // namespace Belle2
A class to represent a digitized signal. Unit is nano second.
Definition: Clock.h:38
A class to represent a bundle of SignalVectors.
Definition: SignalBundle.h:26
const TRGClock * _clock
Clock.
Definition: SignalBundle.h:106
std::string _name
Name.
Definition: SignalBundle.h:103
A class to represent a bundle of digitized signals.
Definition: SignalVector.h:26
A class to represent a digitized signal. Unit is nano second.
Definition: Signal.h:23
A class to represent a state of multi bits.
Definition: State.h:24
unsigned size(void) const
returns bit size.
Definition: State.h:149
static std::string tab(void)
returns tab spaces.
Definition: Debug.cc:47
const TRGSignalVector & set(const TRGState &, int clockPosition)
sets state at given clock.
virtual ~TRGSignalBundle()
Destructor.
TRGState state(int clockPosition) const
returns state at given clock position.
const TRGClock & clock(void) const
returns clock.
Definition: SignalBundle.h:127
const std::string & name(void) const
returns name.
Definition: SignalBundle.h:113
std::vector< int > stateChanges(void) const
returns a list of clock position of state change.
static void enterStage(const std::string &stageName)
Declare that you enter new stage.
Definition: Debug.cc:24
int min(void) const
returns min. clock point.
Definition: Clock.h:194
TRGSignalBundle(const TRGClock &)
Default constructor.
Definition: SignalBundle.cc:32
TRGSignal ored(void) const
returns signal of all ORed.
static int level(void)
returns the debug level.
Definition: Debug.cc:67
bool active(void) const
returns true if there is a signal.
const TRGSignalVector & clockCounter(void) const
returns the clock counter.
Definition: Clock.cc:166
static void leaveStage(const std::string &stageName)
Declare that you leave a stage.
Definition: Debug.cc:34
void dumpCOE(const std::string &fileName="", int start=0, int stop=0) const
makes coe output.
void dump(const std::string &message="", const std::string &pre="") const
dumps contents.
Abstract base class for different kinds of events.
STL namespace.