12import modularAnalysis
as ma
15def add_gdl_trigger(path, SimulationMode=1, FilterEvents=False, simulateT0jitter=False, Belle2Phase="Phase2"):
17 add the gdl module to path
18 @param path module
is added to this path
19 @param SimulationMode the simulation mode
in TSIM, 1: fast simulation,
20 trigger algoritm simulation only, no firmware simulation
21 2: full simulation, both trigger algorithm
and firmware
23 @param FilterEvents
if True only the events that
pass the L1 trigger will
24 survive simulation, the other are discarded.
25 Make sure you do need to filter events before you set
28 trggdl = b2.register_module('TRGGDL')
29 trggdl.param(
'SimulationMode', SimulationMode)
30 trggdl.param(
'Belle2Phase', Belle2Phase)
31 trggdl.param(
'simulateT0jitter', simulateT0jitter)
32 path.add_module(trggdl)
34 ma.applyEventCuts(
'L1Trigger == 1', path)