Belle II Software  release-05-01-25
TRGGDL.cc
1 //-----------------------------------------------------------------------------
2 // $Id$
3 //-----------------------------------------------------------------------------
4 // Filename : TRGGDL.cc
5 // Section : TRG GDL
6 // Owner : Yoshihito Iwasaki, Chunhua Li
7 // Email : yoshihito.iwasaki@kek.jp, chunha.li@unimelb.edu.au
8 //-----------------------------------------------------------------------------
9 // Description : A class to represent GDL.
10 //-----------------------------------------------------------------------------
11 // 0.00 : 2013/12/13 : First version
12 //-----------------------------------------------------------------------------
13 
14 #define TRG_SHORT_NAMES
15 #define TRGGDL_SHORT_NAMES
16 
17 #include <TRandom.h>
18 #include <fstream>
19 #include <stdio.h>
20 #include "trg/trg/Debug.h"
21 #include "trg/trg/Time.h"
22 #include "trg/trg/State.h"
23 #include "trg/trg/Signal.h"
24 #include "trg/trg/Utilities.h"
25 #include "trg/gdl/TRGGDL.h"
26 // framework - DataStore
27 #include <framework/datastore/StoreObjPtr.h>
28 
29 #include <mdst/dataobjects/TRGSummary.h>
30 #include <trg/grl/dataobjects/TRGGRLInfo.h>
31 
32 #include <framework/logging/Logger.h>
33 
34 #include <TH1I.h>
35 
36 #define N_TIMING_REGISTERS 4
37 
38 using namespace std;
39 
40 namespace Belle2 {
46  void ftd_0_01(bool* b, bool* i);
48  //void dotrigger(std::vector<int>& res, std::vector<int> ob);
49 
50  TRGGDL*
51  TRGGDL::_gdl = 0;
52 
53  void
54  (* TRGGDL::_ftd)(bool* b, bool* i) = 0;
55 
56  string
57  TRGGDL::name(void) const
58  {
59  return "TRGGDL";
60  }
61 
62  string
63  TRGGDL::version(void) const
64  {
65  return string("TRGGDL 0.01");
66  }
67 
68  TRGGDL*
69  TRGGDL::getTRGGDL(const string& configFile,
70  unsigned simulationMode,
71  unsigned fastSimulationMode,
72  unsigned firmwareSimulationMode,
73  const std::string& Phase,
74  bool algFromDB,
75  const std::string& algFilePath,
76  int debugLevel)
77  {
78  if (_gdl) {
79  //delete _gdl;
80  _gdl = 0;
81  }
82 
83  if (configFile != "good-bye") {
84  _gdl = new TRGGDL(configFile,
85  simulationMode,
86  fastSimulationMode,
87  firmwareSimulationMode,
88  Phase,
89  algFromDB,
90  algFilePath,
91  debugLevel);
92  } else {
93  cout << "TRGGDL::getTRGGDL ... good-bye" << endl;
94  // delete _gdl;
95  _gdl = 0;
96  }
97 
98  return _gdl;
99  }
100 
101  TRGGDL*
102  TRGGDL::getTRGGDL(void)
103  {
104  if (! _gdl)
105  cout << "TRGGDL::getTRGGDL !!! TRGGDL is not created yet" << endl;
106  return _gdl;
107  }
108 
109  TRGGDL::TRGGDL(const string& configFile,
110  unsigned simulationMode,
111  unsigned fastSimulationMode,
112  unsigned firmwareSimulationMode,
113  const std::string& Phase,
114  bool algFromDB,
115  const std::string& algFilePath,
116  int debugLevel)
117  : _debugLevel(debugLevel),
118  _configFilename(configFile),
119  _simulationMode(simulationMode),
120  _fastSimulationMode(fastSimulationMode),
121  _firmwareSimulationMode(firmwareSimulationMode),
122  _Phase(Phase),
123  _algFilePath(algFilePath),
124  _clock(Belle2_GDL::GDLSystemClock),
125  _offset(15.3),
126  _isb(0),
127  _osb(0),
128  _algFromDB(algFromDB)
129  {
130 
131  if (TRGDebug::level()) {
132  cout << "TRGGDL ... TRGGDL initializing with " << _configFilename
133  << endl
134  << " mode=0x" << hex << _simulationMode << dec << endl;
135  }
136 
137  initialize();
138 
139  if (TRGDebug::level()) {
140  cout << "TRGGDL ... TRGGDL created with " << _configFilename << endl;
141  _clock.dump();
142  }
143 
144  for (int i = 0; i < m_InputBitsDB->getninbit(); i++) {
145  _inpBitNames.push_back(std::string(m_InputBitsDB->getinbitname(i)));
146  }
147 
148  for (int i = 0; i < m_FTDLBitsDB->getnoutbit(); i++) {
149  _oupBitNames.push_back(std::string(m_FTDLBitsDB->getoutbitname(i)));
150  }
151 
152  }
153 
154  void
156  {
157  if (_debugLevel > 19) {
158  for (int i = 0; i < m_InputBitsDB->getninbit(); i++) {
159  B2DEBUG(20, "TRGGDL::initialize, inputBits: " << i << ", " << m_InputBitsDB->getinbitname(i));
160  }
161  for (int i = 0; i < m_FTDLBitsDB->getnoutbit(); i++) {
162  B2DEBUG(20, "TRGGDL::initialize, outputBits: " << i << ", " << m_FTDLBitsDB->getoutbitname(i));
163  }
164  for (int i = 0; i < db_algs->getnalgs(); i++) {
165  B2DEBUG(20, "TRGGDL::initialize, algs: " << i << ", " << db_algs->getalg(i));
166  }
167  }
168  //if it is firmware simulation, do the cofigurnation
169  //fastsimulation doesn't use the configuration currently
170  if (_simulationMode == 2) configure();
171  }
172 
173  void
175  {
176  }
177 
178  void
179  TRGGDL::dump(const string& msg) const
180  {
181  if (msg.find("name") != string::npos ||
182  msg.find("version") != string::npos ||
183  msg.find("detail") != string::npos ||
184  msg == "") {
185  }
186  if (msg.find("detail") != string::npos ||
187  msg.find("state") != string::npos) {
188  cout << "Debug Level=" << _debugLevel;
189  cout << endl;
190  }
191  }
192 
193  void
195  {
196  }
197 
198  void
200  {
201  }
202 
203  void
205  {
206  /*
207  TRGDebug::enterStage("TRGGDL update");
208 
209  if (TRGDebug::level())
210  cout << TRGDebug::tab() << name() << " do nothing..." << endl;
211 
212  TRGDebug::leaveStage("TRGGDL update");
213  */
214  }
215 
217  {
218  clear();
219  }
220 
221  void
223  {
224  const bool fast = (_simulationMode == 1);
225  const bool firm = (_simulationMode == 2);
226  const bool data = (_simulationMode == 3);
227  if (fast)
228  fastSimulation();
229  if (firm)
231  if (data)
232  dataSimulation();
233  }
234 
235  void
237  {
238  B2DEBUG(20, "TRGGDL::fastSimulation starts.");
239  TRGDebug::enterStage("TRGGDL fastSim");
240 
241  if (TRGDebug::level())
242  cout << TRGDebug::tab() << name() << " do nothing..." << endl;
243 
244  TRGDebug::leaveStage("TRGGDL fastSim");
245 
246  if (!m_InputBitsDB) B2INFO("no database of gdl input bits");
247  int N_InputBits = m_InputBitsDB->getninbit();
248  if (!m_FTDLBitsDB) B2INFO("no database of gdl ftdl bits");
249  int N_OutputBits = m_FTDLBitsDB->getnoutbit();
250  if (!m_PrescalesDB) B2INFO("no database of gdl prescale");
251 
252  StoreObjPtr<TRGSummary> GDLResult;
253  if (GDLResult) {
254  B2WARNING("TRGGDL::fastSimulation(): TRGSummary exist already, check it!!!!");
255  return;
256  } else {
257  GDLResult.create();
258  StoreObjPtr<TRGGRLInfo> grlinfo("TRGGRLObjects");
259  if (!grlinfo) {
260  B2WARNING("TRGGRLInfo doesn't exist!!!!");
261  return;
262  } else {
263  if (_debugLevel > 89) printf("TRGGDL:TRGGRLInfo found.\n");
264  }
265 
266  _inpBits.clear();
267  int input_summary = 0;
268  for (int i = 0; i < N_InputBits; i++) {
269  if (_debugLevel > 89) printf("TRGGDL:ABC:i(%d)\n", i);
270  if ((i % 32) == 0) {
271  if (i > 0) {
272  GDLResult->setInputBits(i / 32 - 1, input_summary);
273  }
274  input_summary = 0;
275  }
276  if (grlinfo->getInputBits(i)) input_summary |= (1 << (i % 32));
277  _inpBits.push_back(grlinfo->getInputBits(i));
278  if (i == N_InputBits - 1) {
279  GDLResult->setInputBits(i / 32, input_summary);
280  }
281  }
282 
283  int L1Summary = 0;
284  int L1Summary_psnm = 0;
285  std::string str;
286  std::vector<std::string> algs;
287  std::ifstream isload(_algFilePath.c_str(), std::ios::in);
288  int index = 0;
289  while (std::getline(isload, str)) {
290  algs.push_back(str);
291  index++;
292  }
293  isload.close();
294 
295  for (int i = 0; i < N_OutputBits; i++) {
296  if (_debugLevel > 89) printf("TRGGDL:ABB:i(%d)\n", i);
297  if ((i % 32) == 0) {
298  if (i > 0) {
299  GDLResult->setFtdlBits(i / 32 - 1, L1Summary);
300  GDLResult->setPsnmBits(i / 32 - 1, L1Summary_psnm);
301  }
302  L1Summary = 0;
303  L1Summary_psnm = 0;
304  }
305  std::string alg = _algFromDB ? db_algs->getalg(i) : algs[i];
306  if (_debugLevel > 89) printf("TRGGDL:i(%d), alg(%s)\n", i, db_algs->getalg(i).c_str());
307  if (isFiredFTDL(_inpBits, alg)) {
308  L1Summary |= (1 << (i % 32));
309  if (doprescale(m_PrescalesDB->getprescales(i))) {
310  L1Summary_psnm |= (1 << (i % 32));
311  }
312  }
313  GDLResult->setPreScale((i / 32), (i % 32), m_PrescalesDB->getprescales(i));
314  if (i == N_OutputBits - 1) {
315  GDLResult->setFtdlBits(i / 32, L1Summary);
316  GDLResult->setPsnmBits(i / 32, L1Summary_psnm);
317  }
318  }
319  }
320  }
321 
322  void
324  {
325 // B2DEBUG(20,"TRGGDL::dataSimulation starts.");
327  /*
328  unsigned _exp = bevt->getExperiment();
329  unsigned _run = bevt->getRun();
330  */
331  if (_debugLevel > 9) printf("TRGGDL:dataSimulation Start\n");
332  unsigned _evt = bevt->getEvent();
333 // TRGDebug::enterStage("TRGGDL dataSim");
334 
335 // if (TRGDebug::level())
336 // cout << TRGDebug::tab() << name() << " do nothing..." << endl;
337 
338  if (!m_InputBitsDB) B2INFO("no database of gdl input bits");
339  int N_InputBits = m_InputBitsDB->getninbit();
340  if (!m_FTDLBitsDB) B2INFO("no database of gdl ftdl bits");
341  int N_OutputBits = m_FTDLBitsDB->getnoutbit();
342  if (!m_PrescalesDB) B2INFO("no database of gdl prescale");
343 
344  if (_debugLevel > 19)
345  printf("TRGGDL:N_InputBits(%d), N_OutputBits(%d)\n", N_InputBits, N_OutputBits);
346 
347  StoreObjPtr<TRGSummary> GDLResult;
348  if (! GDLResult) {
349  B2WARNING("TRGGDL::dataSimulation(): TRGSummary not found. Check it!!!!");
350  return;
351  } else {
352 
353  if (_debugLevel > 89) printf("TRGGDL:TRGSummary Found.\n");
354  _inpBits.clear();
355  _ftdBits.clear();
356  _psnBits.clear();
357  for (int i = 0; i < N_InputBits; i++) {
358  _inpBits.push_back(GDLResult->testInput(i));
359  }
360 
361  if (_algFromDB) {
362 
363  int L1Summary = 0;
364  int L1Summary_psnm = 0;
365 
366  for (int i = 0; i < N_OutputBits; i++) {
367  bool ftdl_fired = isFiredFTDL(_inpBits, db_algs->getalg(i));
368  bool psnm_fired = false;
369  _ftdBits.push_back(ftdl_fired);
370  if (ftdl_fired) {
371  L1Summary |= (1 << i);
372  if (doprescale(m_PrescalesDB->getprescales(i))) {
373  L1Summary_psnm |= (1 << i);
374  psnm_fired = true;
375  }
376  }
377  psnm_fired ? _psnBits.push_back(true) : _psnBits.push_back(false);
378  GDLResult->setPreScale((i / 32), (i % 32), m_PrescalesDB->getprescales(i));
379  if (! strcmp(m_FTDLBitsDB->getoutbitname(i), "hie")) {
380  if (_debugLevel == 971 && ftdl_fired) {
381  int i_ehigh = m_InputBitsDB->getinbitnum("ehigh");
382  int i_bha_veto = m_InputBitsDB->getinbitnum("bha_veto");
383  printf("TRGGDL:hie:i=%d,evt=%d,ps=%d,ehigh=%d,bha_veto=%d,ftdl_fired=%d,psnm_fired=%d,i_ehigh=%d,i_bha_veto=%d,obitname=%s\n",
384  i, _evt, m_PrescalesDB->getprescales(i),
385  _inpBits[i_ehigh] ? 1 : 0,
386  _inpBits[i_bha_veto] ? 1 : 0,
387  ftdl_fired ? 1 : 0,
388  psnm_fired ? 1 : 0,
389  i_ehigh,
390  i_bha_veto,
391  m_FTDLBitsDB->getoutbitname(i));
392  }
393  }
394  }
395 
396  } else {
397 
398  int L1Summary = 0;
399  int L1Summary_psnm = 0;
400  std::string str;
401  std::vector<std::string> algs;
402  std::ifstream isload(_algFilePath.c_str(), std::ios::in);
403  int index = 0;
404  while (std::getline(isload, str)) {
405  algs.push_back(str);
406  index++;
407  }
408  isload.close();
409 
410  for (int i = 0; i < N_OutputBits; i++) {
411  bool ftdl_fired = isFiredFTDL(_inpBits, algs[i]);
412  bool psnm_fired = false;
413  _ftdBits.push_back(ftdl_fired);
414  if (ftdl_fired) {
415  L1Summary |= (1 << i);
416  if (doprescale(m_PrescalesDB->getprescales(i))) {
417  L1Summary_psnm |= (1 << i);
418  psnm_fired = true;
419  }
420  }
421  psnm_fired ? _psnBits.push_back(true) : _psnBits.push_back(false);
422  GDLResult->setPreScale((i / 32), (i % 32), m_PrescalesDB->getprescales(i));
423  }
424 
425  }
426 
427 
428  }
429  }
430 
431  bool
432  TRGGDL::isFiredFTDL(std::vector<bool> input, std::string alg)
433  {
434  if (alg.length() == 0) return true;
435  const char* cst = alg.c_str();
436  bool reading_word = false;
437  bool result_the_term = true; // init value must be true
438  bool not_flag = false;
439  unsigned begin_word = 0;
440  unsigned word_length = 0;
441  // notation steeing side must follow
442  // no blank between '!' and word
443  for (unsigned i = 0; i < alg.length(); i++) {
444  if (('0' <= cst[i] && cst[i] <= '9') ||
445  ('_' == cst[i]) || ('!' == cst[i])) {
446  if (reading_word) { // must not be '!'
447  word_length++;
448  if (i == alg.length() - 1) {
449  bool fired = input[atoi(alg.substr(begin_word, word_length).c_str())];
450  B2DEBUG(20,
451  alg.substr(begin_word, word_length).c_str()
452  << "(" << fired << ")");
453  if (((!not_flag && fired) || (not_flag && !fired)) && result_the_term) {
454  return true;
455  }
456  }
457  } else {
458  // start of new word
459  reading_word = true;
460  if ('!' == cst[i]) {
461  begin_word = i + 1;
462  not_flag = true;
463  word_length = 0;
464  } else {
465  begin_word = i;
466  not_flag = false;
467  word_length = 1;
468  if (i == alg.length() - 1) {
469  // one char bit ('f',...) comes end of conditions, 'xxx+f'
470  bool fired = input[atoi(alg.substr(begin_word, word_length).c_str())];
471  B2DEBUG(20,
472  alg.substr(begin_word, word_length).c_str()
473  << "(" << fired << ")");
474  if (((!not_flag && fired) || (not_flag && !fired)) && result_the_term) {
475  return true;
476  }
477  }
478  }
479  }
480  } else if ('+' == cst[i] || i == alg.length() - 1) {
481  // End of the term.
482  if (reading_word) { // 'xxx+'
483  if (result_the_term) {
484  bool fired = input[atoi(alg.substr(begin_word, word_length).c_str())];
485  B2DEBUG(20,
486  alg.substr(begin_word, word_length).c_str()
487  << "(" << fired << ")");
488  if ((!not_flag && fired) || (not_flag && !fired)) {
489  return true;
490  } else {
491  // this term is denied by the latest bit
492  }
493  } else {
494  // already false.
495  }
496  reading_word = false;
497  } else {
498  // prior char is blank, 'xxx +'
499  if (result_the_term) {
500  return true;
501  } else {
502  // already false
503  }
504  }
505  result_the_term = true; // go to next term
506  } else {
507  // can be blank (white space) or any delimiter.
508  if (reading_word) {
509  // end of a word, 'xxxx '
510  reading_word = false;
511  if (result_the_term) {
512  // worth to try
513  bool fired = input[atoi(alg.substr(begin_word, word_length).c_str())];
514  B2DEBUG(20,
515  alg.substr(begin_word, word_length).c_str()
516  << "(" << fired << ")");
517  if ((!not_flag && fired) || (not_flag && !fired)) {
518  // go to next word
519  } else {
520  result_the_term = false;
521  }
522  } else {
523  // already false
524  }
525  reading_word = false;
526  } else {
527  // 2nd blank 'xx ' or leading blanck '^ '
528  }
529  }
530  }
531  return false;
532  }
533 
534  bool TRGGDL::doprescale(int f)
535  {
536  if (f == 0) return false;
537  if (f == 1) return true;
538  double ran = gRandom->Uniform(f);
539  return (ceil(ran) == f);
540  }
541 
542 
543  void
545  {
546 // TRGDebug::enterStage("TRGGDL firmSim");
547 
548 // if (TRGDebug::level())
549 // cout << TRGDebug::tab() << "Making dummy input signals" << endl;
550 
551  //...Clear signal bundles...
552  if (_isb) {
553  for (unsigned i = 0; i < _isb->size(); i++)
554  delete(* _isb)[i];
555  delete _isb;
556  }
557  if (_osb) {
558  for (unsigned i = 0; i < _osb->size(); i++)
559  delete(* _osb)[i];
560  delete _osb;
561  }
562  if (_tsb) {
563  for (unsigned i = 0; i < _tsb->size(); i++)
564  delete(* _tsb)[i];
565  delete _tsb;
566  }
567  if (_tosb) {
568  for (unsigned i = 0; i < _tosb->size(); i++)
569  delete(* _tosb)[i];
570  delete _tosb;
571  }
572 
573  //...Input bits...
574  const unsigned nInput = _input.size();
575  TRGSignalVector& input = * new TRGSignalVector(name() + "InputSignals",
576  _clock);
577  TRGSignalVector& timing = * new TRGSignalVector(name() + "TimingSignals",
578  _clock);
579  for (unsigned i = 0; i < nInput; i++) {
580 
581  TRGSignal s;
582 
583  //...Create dummy timing signal for even number input bits...
584  if ((i % 2) == 0) {
585  int tdcCount = 100;
586  TRGTime rise = TRGTime(tdcCount, true, _clock, _input[i]);
587  TRGTime fall = rise;
588  fall.shift(1).reverse();
589  s = TRGSignal(rise & fall);
590  s.name(_input[i]);
591  }
592 
593  //...Create dummy timing signal for odd number input bits...
594  else {
595  int tdcCount = 130;
596  TRGTime rise = TRGTime(tdcCount, true, _clock, _input[i]);
597  TRGTime fall = rise;
598  fall.shift(1).reverse();
599  s = TRGSignal(rise & fall);
600  s.name(_input[i]);
601  }
602 
603  //...Add to a signal vector...
604  input += s;
605 
606  //...Timing signal...
607  bool t =
608  (i == 14) || (i == 15) || (i == 16) || (i == 17) ||
609  (i == 41) || (i == 42) || (i == 43) || (i == 44) ||
610  (i == 49) || (i == 50) || (i == 51) || (i == 52) || (i == 53);
611  if (t)
612  timing += s;
613  }
614 
615  //...Make input signal bundle...
616  const string ni = name() + "InputSignalBundle";
617  _isb = new TRGSignalBundle(ni, _clock);
618  _isb->push_back(& input);
619 
620  //...Make output signal bundle...
621  const string no = name() + "OutputSignalBundle";
622  _osb = new TRGSignalBundle(no,
623  _clock,
624  * _isb,
625  14,
627 
628  //...Timing signal bundle...
629  TRGSignalVector& ftd = * new TRGSignalVector(name() + "FTD", _clock);
630 // ftd += (* ((* _osb)[0])[13]);
631 // ftd += * (* _osb)[0][13];
632  TRGSignal ddddd = (* (* _osb)[0])[13];
633  ftd += ddddd;
634 
635  const string nt = name() + "TimingSignalBundle";
636  _tsb = new TRGSignalBundle(nt, _clock);
637  _tsb->push_back(& timing);
638  _tsb->push_back(& ftd);
639 
640  //...Timing out signal bundle...
641  const string nto = name() + "TimingOutSignalBundle";
642  _tosb = new TRGSignalBundle(nto,
643  _clock,
644  * _tsb,
645  3,
646  7,
648 
649  if (TRGDebug::level()) {
650  if (input.active()) {
651  _isb->dump("detail", TRGDebug::tab());
652  _osb->dump("detail", TRGDebug::tab());
653  _tsb->dump("detail", TRGDebug::tab());
654  _tosb->dump("detail", TRGDebug::tab());
655  }
656  }
657 
658  TRGDebug::leaveStage("TRGGDL firmSim");
659  }
660 
661  void
663  {
664 
665  //...Open input data definition...
666  const string fni = _configFilename + ".inp";
667  ifstream infile(fni.c_str(), ios::in);
668  if (infile.fail()) {
669  cout << "TRGGDL !!! can not open file : " << fni << endl;
670  return;
671  }
672  getInput(infile);
673  infile.close();
674 
675  //...Open output data definition...
676  const string fno = _configFilename + ".oup";
677  ifstream outfile(fno.c_str(), ios::in);
678  if (outfile.fail()) {
679  cout << "TRGGDL !!! can not open file : " << fno << endl;
680  return;
681  }
682  getOutput(outfile);
683  outfile.close();
684 
685  //...Open algorithm data definition...
686  const string fna = _configFilename + ".alg";
687  ifstream algfile(fna.c_str(), ios::in);
688  if (algfile.fail()) {
689  cout << "TRGGDL !!! can not open file : " << fna << endl;
690  return;
691  }
692  getAlgorithm(algfile);
693  algfile.close();
694 
695  //...FTD function...
696  string ftd = _configFilename;
697  string::size_type s = ftd.find_last_of("/");
698  if (s != string::npos)
699  ftd = ftd.substr(s + 1);
700  if (ftd == "ftd_0.01") {
701  _ftd = ftd_0_01;
702  }
703 
704  //...Summary...
705  if (TRGDebug::level()) {
706  cout << "TRGGDL Config file = " << _configFilename << endl;
707  cout << " ftd=" << ftd << endl;
708  cout << "TRGGDL Input Bits" << endl;
709  for (unsigned i = 0; i < _input.size(); i++)
710  cout << TRGDebug::tab(4) << i << " : " << _input[i] << endl;
711  cout << "TRGGDL Output Bits" << endl;
712  for (unsigned i = 0; i < _output.size(); i++)
713  cout << TRGDebug::tab(4) << i << " : " << _output[i]
714  << " : " << _algorithm[i] << endl;
715  }
716  }
717 
718  void
719  TRGGDL::getInput(ifstream& ifs)
720  {
721  if (TRGDebug::level()) {
722  cout << "TRGGDL::getInput ... reading input data" << endl;
723  }
724 
725  char b[800];
726  unsigned lines = 0;
727  while (! ifs.eof()) {
728  ifs.getline(b, 800);
729 
730  //...The first word should be input bit number...
731  // const string w0 = TRGUtilities::carstring(b);
732 
733  //...Bit name...
734  string cdr = TRGUtilities::cdrstring(b);
735  const string w1 = TRGUtilities::carstring(cdr);
736 
737  if (w1.size())
738  _input.push_back(w1);
739 
740  ++lines;
741  }
742 
743  }
744 
745  void
746  TRGGDL::getOutput(ifstream& ifs)
747  {
748 
749  if (TRGDebug::level()) {
750  cout << "TRGGDL::getOutput ... reading output data" << endl;
751  }
752 
753  char b[800];
754  unsigned lines = 0;
755  while (! ifs.eof()) {
756  ifs.getline(b, 800);
757 
758  //...The first word should be input bit number...
759  // const string w0 = TRGUtilities::carstring(b);
760 
761  //...Bit name...
762  string cdr = TRGUtilities::cdrstring(b);
763  const string w1 = TRGUtilities::carstring(cdr);
764 
765  if (w1.size())
766  _output.push_back(w1);
767 
768  ++lines;
769  }
770 
771  }
772 
773  void
774  TRGGDL::getAlgorithm(ifstream& ifs)
775  {
776 
777  if (TRGDebug::level()) {
778  cout << "TRGGDL::getAlgorithm ... reading algorithm data" << endl;
779  }
780 
781  char b[800];
782  unsigned lines = 0;
783  while (! ifs.eof()) {
784  ifs.getline(b, 800);
785 
786  //...The first word should be input bit number...
787  // const string w0 = TRGUtilities::carstring(b);
788 
789  //...':'...
790  string cdr = TRGUtilities::cdrstring(b);
791  // const string w1 = TRGUtilities::carstring(cdr);
792 
793  //...Algorithm...
794  cdr = TRGUtilities::cdrstring(cdr);
795  const string w2 = cdr;
796 
797  if (w2.size())
798  _algorithm.push_back(w2);
799 
800  ++lines;
801  }
802 
803  }
804 
805  TRGState
807  {
808 
809  //...Prepare states for output...
810  TRGState s(14);
811 
812  //...Set up bool array...
813  bool* in = new bool[input.size()];
814  bool* ou = new bool[14];
815  input.copy2bool(in);
816 
817  // //...Simulate output bit 4...
818  // s.set(4, in[15] & (! in[18]) & in[33] & (! in[51]));
819 
820  // //...Simulate output bit 10...
821  // s.set(10, in[46]);
822 
823  //...FTD logic...
824  _ftd(ou, in);
825  bool active = false;
826  for (unsigned i = 0; i < 13; i++) {
827  if (ou[i])
828  active = true;
829  s.set(i, ou[i]);
830  }
831  if (active)
832  s.set(13, true);
833 
834  if (TRGDebug::level()) {
835  input.dump("detail", TRGDebug::tab(4) + "GDL in ");
836  s.dump("detail", TRGDebug::tab(4) + "GDL out ");
837  }
838 
839  //...Termination...
840  delete[] in;
841  delete[] ou;
842  return s;
843  }
844 
845  TRGState
847  TRGState& reg,
848  bool& active)
849  {
850 
851  //...Prepare registers...
852  // reg[0] := timing logic active, NOT USED
853  // reg[3:1] := state (0 to 7)
854  // reg[6:4] := counter after timing logic active
855 
856  // reg[1] := waiting for timing of TOP, ECL, and CDC
857  // reg[2] := TOP timing active
858  // reg[3] := ECL timing active
859  // reg[4] := CDC timing active
860  // reg[7:5] := remaining count to issue timing signal
861 
862 
863 
864  //...Input preparations...
865  // Assuming ftl_0.01
866  // Last bit is additional FTD signal
867  bool in[14];
868 
869  //...CDC...
870  in[0] = input[0];
871  in[1] = input[1];
872  in[2] = input[2];
873  in[3] = input[3];
874  /*
875  bool cdc = in[0];
876  bool * cdct = & in[1];
877  */
878 
879  //...ECL...
880  in[4] = input[4];
881  in[5] = input[5];
882  in[6] = input[6];
883  in[7] = input[7];
884  /*
885  bool ecl = in[4];
886  bool * eclt = & in[5];
887  */
888 
889  //...TOP...
890  in[8] = input[8];
891  in[9] = input[9];
892  in[10] = input[10];
893  in[11] = input[11];
894  in[12] = input[12];
895  /*
896  bool top = in[8];
897  bool * topt = & in[9];
898  */
899 
900  //...FTD...
901  in[13] = input[13];
902  bool ftd = in[13];
903 
904  //...Get state info...
905  unsigned state = unsigned(reg.subset(1, 3));
906  unsigned count = unsigned(reg.subset(4, 3));
907 
908  //...State machine...
909  bool timing = false;
910  unsigned source = 0;
911  if (state == 0) {
912  if (ftd) {
913  active = 1;
914  state = 1;
915  count = 1;
916  } else {
917  active = 0;
918  }
919  } else if (state == 1) {
920  if (count == 7) {
921  active = 0;
922  state = 0;
923  timing = true;
924  } else {
925  active = 1;
926  ++count;
927  }
928  }
929 
930  //...Set registers...
931  reg.set(1, 3, state);
932  reg.set(4, 3, count);
933 
934  //...Output...
935  TRGState out(3);
936  out.set(0, 1, timing);
937  out.set(1, 2, source);
938 
939  if (TRGDebug::level()) {
940  input.dump("detail", TRGDebug::tab(4) + "Timing in,");
941  reg.dump("detail", TRGDebug::tab(4) + "Registers,");
942  cout << TRGDebug::tab(4) << "ftd,active,state,count=" << ftd << ","
943  << active << "," << state
944  << "," << count << endl;
945 
946  out.dump("detail", TRGDebug::tab(4) + "Timing out,");
947  }
948 
949  //...Termination...
950  return out;
951  }
952 
953  void
955  {
956  for (std::size_t i = 0; i < _inpBits.size(); i++) {
957  if (_inpBits[i]) h->Fill(i);
958  }
959  }
960 
961  void
963  {
964  for (std::size_t i = 0; i < _ftdBits.size(); i++) {
965  if (_ftdBits[i]) h->Fill(i);
966  }
967  }
968 
969  void
971  {
972  for (std::size_t i = 0; i < _psnBits.size(); i++) {
973  if (_psnBits[i]) h->Fill(i);
974  }
975  }
976 
978 } // namespace Belle2
Belle2::TRGGDL::getInput
void getInput(std::ifstream &ifs)
Read input data definition.
Definition: TRGGDL.cc:719
Belle2::TRGSignal
A class to represent a digitized signal. Unit is nano second.
Definition: Signal.h:28
Belle2::TRGGDL::getAlgorithm
void getAlgorithm(std::ifstream &ifs)
Read algorithm data definition.
Definition: TRGGDL.cc:774
Belle2::TRGTime::shift
TRGTime & shift(int unit)
delays by clock unit.
Definition: Time.h:168
Belle2::TRGGDL::_input
std::vector< std::string > _input
Input names.
Definition: TRGGDL.h:238
Belle2::TRGGDL::decision
static TRGState decision(const TRGState &input)
Makes bit pattern(state) using input bit pattern(state).
Definition: TRGGDL.cc:806
Belle2::TRGGDL::firmwareSimulation
void firmwareSimulation(void)
Firmware simulation.
Definition: TRGGDL.cc:544
Belle2::TRGDebug::level
static int level(void)
returns the debug level.
Definition: Debug.cc:72
Belle2::TRGState::subset
TRGState subset(unsigned i, unsigned n) const
returns subset from i with n bits.
Definition: State.cc:362
Belle2::TRGGDL::getOutput
void getOutput(std::ifstream &ifs)
Read output data definition.
Definition: TRGGDL.cc:746
Belle2::TRGGDL::accumulatePsn
void accumulatePsn(TH1I *)
Accumulate bit info in histogram.
Definition: TRGGDL.cc:970
Belle2::TRGGDL::accumulateInp
void accumulateInp(TH1I *)
Accumulate bit info in histogram.
Definition: TRGGDL.cc:954
Belle2::TRGGDL::_configFilename
std::string _configFilename
GDL configuration filename.
Definition: TRGGDL.h:211
Belle2::TRGGDL::dataSimulation
void dataSimulation(void)
Data simulation.
Definition: TRGGDL.cc:323
Belle2::TRGGDL::dump
void dump(const std::string &message) const
dumps debug information.
Definition: TRGGDL.cc:179
Belle2::TRGGDL::simulate
void simulate(void)
fast trigger simulation.
Definition: TRGGDL.cc:222
Belle2::TRGGDL::fastClear
void fastClear(void)
clears TRGGDL information.
Definition: TRGGDL.cc:199
Belle2::TRGState
A class to represent a state of multi bits.
Definition: State.h:29
Belle2::TRGGDL::_tsb
TRGSignalBundle * _tsb
Timing input signal bundle.
Definition: TRGGDL.h:253
Belle2::TRGGDL
The instance of TRGGDL is a singleton.
Definition: TRGGDL.h:48
Belle2::TRGGDL::name
std::string name(void) const
returns name.
Definition: TRGGDL.cc:57
Belle2::TRGGDL::_ftd
static void(* _ftd)(bool *out, bool *in)
Function to simulate final trigger decision.
Definition: TRGGDL.h:145
Belle2::TRGGDL::_algorithm
std::vector< std::string > _algorithm
Algorithm.
Definition: TRGGDL.h:244
Belle2::TRGSignalBundle
A class to represent a bundle of SignalVectors.
Definition: SignalBundle.h:31
Belle2::TRGGDL::_output
std::vector< std::string > _output
Output names.
Definition: TRGGDL.h:241
Belle2::TRGGDL::_osb
TRGSignalBundle * _osb
Output signal bundle.
Definition: TRGGDL.h:250
Belle2::TRGGDL::~TRGGDL
virtual ~TRGGDL()
Destructor.
Definition: TRGGDL.cc:216
Belle2::TRGClock::dump
void dump(const std::string &message="", const std::string &pre="") const
dumps contents.
Definition: Clock.cc:93
Belle2::TRGGDL::update
void update(bool mcAnalysis=true)
updates TRGGDL information.
Definition: TRGGDL.cc:204
Belle2::TRGState::set
const TRGState & set(unsigned position, bool state=true)
sets state at bit i.
Definition: State.h:309
Belle2::TRGGDL::timingDecision
static TRGState timingDecision(const TRGState &input, TRGState &registers, bool &logicStillActive)
Makes timing decision.
Definition: TRGGDL.cc:846
Belle2::TRGGDL::_debugLevel
int _debugLevel
Debug level.
Definition: TRGGDL.h:208
Belle2
Abstract base class for different kinds of events.
Definition: MillepedeAlgorithm.h:19
Belle2::StoreObjPtr
Type-safe access to single objects in the data store.
Definition: ParticleList.h:33
Belle2::TRGUtilities::carstring
static std::string carstring(const std::string &s)
CERNLIB car.
Belle2::TRGGDL::_clock
const TRGClock & _clock
GDL trigger system clock.
Definition: TRGGDL.h:229
Belle2::TRGGDL::_tosb
TRGSignalBundle * _tosb
Timing output signal bundle.
Definition: TRGGDL.h:256
Belle2::TRGDebug::tab
static std::string tab(void)
returns tab spaces.
Definition: Debug.cc:52
Belle2::TRGGDL::accumulateFtd
void accumulateFtd(TH1I *)
Accumulate bit info in histogram.
Definition: TRGGDL.cc:962
Belle2::TRGGDL::clear
void clear(void)
clears all TRGGDL information.
Definition: TRGGDL.cc:194
Belle2::TRGGDL::fastSimulation
void fastSimulation(void)
Fast simulation.
Definition: TRGGDL.cc:236
Belle2::TRGGDL::terminate
void terminate(void)
terminates when run is finished
Definition: TRGGDL.cc:174
Belle2::TRGGDL::_simulationMode
unsigned _simulationMode
Simulation mode.
Definition: TRGGDL.h:214
Belle2::TRGDebug::leaveStage
static void leaveStage(const std::string &stageName)
Declare that you leave a stage.
Definition: Debug.cc:39
Belle2::TRGDebug::enterStage
static void enterStage(const std::string &stageName)
Declare that you enter new stage.
Definition: Debug.cc:29
Belle2::TRGTime
A class to represent a signal timing in the trigger system.
Definition: Time.h:30
Belle2::TRGGDL::configure
void configure(void)
configures trigger modules for firmware simulation.
Definition: TRGGDL.cc:662
Belle2::TRGGDL::m_InputBitsDB
DBObjPtr< TRGGDLDBInputBits > m_InputBitsDB
Data base of GDL input bits.
Definition: TRGGDL.h:259
Belle2::TRGGDL::_isb
TRGSignalBundle * _isb
Input signal bundle.
Definition: TRGGDL.h:247
Belle2::TRGSignalVector
A class to represent a bundle of digitized signals.
Definition: SignalVector.h:31
Belle2::TRGTime::reverse
TRGTime & reverse(void)
reverse edge.
Definition: Time.h:146
Belle2::TRGUtilities::cdrstring
static std::string cdrstring(const std::string &s)
CERNLIB cdr.
Belle2::TRGGDL::initialize
void initialize(void)
initializes GDL.
Definition: TRGGDL.cc:155