Belle II Software  release-05-01-25
trggdlSummaryModule.cc
1 //---------------------------------------------------------------
2 // $Id$
3 //---------------------------------------------------------------
4 // Filename : trggdlSummaryModule.cc
5 // Section : TRG GDL Summary
6 // Owner :
7 // Email :
8 //---------------------------------------------------------------
9 // Description : A trigger module for TRG GDL
10 //---------------------------------------------------------------
11 // 1.00 : 2017/05/08 : First version
12 //---------------------------------------------------------------
13 #include <trg/gdl/modules/trggdlSummary/trggdlSummaryModule.h>
14 
15 #include <framework/datastore/StoreArray.h>
16 
17 #include <mdst/dataobjects/TRGSummary.h>
18 
19 #include <framework/database/DBObjPtr.h>
20 #include <mdst/dbobjects/TRGGDLDBInputBits.h>
21 #include <mdst/dbobjects/TRGGDLDBFTDLBits.h>
22 
23 #include <string.h>
24 
25 
26 using namespace Belle2;
27 using namespace GDL;
28 
29 REG_MODULE(TRGGDLSummary);
30 
31 TRGGDLSummaryModule::TRGGDLSummaryModule()
32  : Module::Module()
33 {
34 
35  setDescription("Fill experiment data to TRGSummary");
36  setPropertyFlags(c_ParallelProcessingCertified);
37  addParam("debugLevel", _debugLevel, "Debug Level", 0);
38 
39 }
40 
41 void TRGGDLSummaryModule::initialize()
42 {
43 
44  if (_debugLevel > 9) printf("TRGGDLSummaryModule::initialize() start\n");
45 
46  GDLResult.registerInDataStore();
47  for (int i = 0; i < 320; i++) {
48  LeafBitMap[i] = m_unpacker->getLeafMap(i);
49  }
50  for (int i = 0; i < 320; i++) {
51  strcpy(LeafNames[i], m_unpacker->getLeafnames(i));
52  }
53 
54  _e_timtype = 0;
55  _e_rvcout = 0;
56  for (int i = 0; i < 10; i++) {
57  ee_psn[i] = 0;
58  ee_ftd[i] = 0;
59  ee_itd[i] = 0;
60  }
61  for (int i = 0; i < 320; i++) {
62  if (strcmp(LeafNames[i], "timtype") == 0)_e_timtype = LeafBitMap[i];
63  if (strcmp(LeafNames[i], "rvcout") == 0) _e_rvcout = LeafBitMap[i];
64  if (strcmp(LeafNames[i], "psn0") == 0) ee_psn[0] = LeafBitMap[i];
65  if (strcmp(LeafNames[i], "psn1") == 0) ee_psn[1] = LeafBitMap[i];
66  if (strcmp(LeafNames[i], "psn2") == 0) ee_psn[2] = LeafBitMap[i];
67  if (strcmp(LeafNames[i], "psn3") == 0) ee_psn[3] = LeafBitMap[i];
68  if (strcmp(LeafNames[i], "psn4") == 0) ee_psn[4] = LeafBitMap[i];
69  if (strcmp(LeafNames[i], "psn5") == 0) ee_psn[5] = LeafBitMap[i];
70  if (strcmp(LeafNames[i], "psn6") == 0) ee_psn[6] = LeafBitMap[i];
71  if (strcmp(LeafNames[i], "psn7") == 0) ee_psn[7] = LeafBitMap[i];
72  if (strcmp(LeafNames[i], "psn8") == 0) ee_psn[8] = LeafBitMap[i];
73  if (strcmp(LeafNames[i], "psn9") == 0) ee_psn[9] = LeafBitMap[i];
74  if (strcmp(LeafNames[i], "ftd0") == 0) ee_ftd[0] = LeafBitMap[i];
75  if (strcmp(LeafNames[i], "ftd1") == 0) ee_ftd[1] = LeafBitMap[i];
76  if (strcmp(LeafNames[i], "ftd2") == 0) ee_ftd[2] = LeafBitMap[i];
77  if (strcmp(LeafNames[i], "ftd3") == 0) ee_ftd[3] = LeafBitMap[i];
78  if (strcmp(LeafNames[i], "ftd4") == 0) ee_ftd[4] = LeafBitMap[i];
79  if (strcmp(LeafNames[i], "ftd5") == 0) ee_ftd[5] = LeafBitMap[i];
80  if (strcmp(LeafNames[i], "ftd6") == 0) ee_ftd[6] = LeafBitMap[i];
81  if (strcmp(LeafNames[i], "ftd7") == 0) ee_ftd[7] = LeafBitMap[i];
82  if (strcmp(LeafNames[i], "ftd8") == 0) ee_ftd[8] = LeafBitMap[i];
83  if (strcmp(LeafNames[i], "ftd9") == 0) ee_ftd[9] = LeafBitMap[i];
84  if (strcmp(LeafNames[i], "itd0") == 0) ee_itd[0] = LeafBitMap[i];
85  if (strcmp(LeafNames[i], "itd1") == 0) ee_itd[1] = LeafBitMap[i];
86  if (strcmp(LeafNames[i], "itd2") == 0) ee_itd[2] = LeafBitMap[i];
87  if (strcmp(LeafNames[i], "itd3") == 0) ee_itd[3] = LeafBitMap[i];
88  if (strcmp(LeafNames[i], "itd4") == 0) ee_itd[4] = LeafBitMap[i];
89  if (strcmp(LeafNames[i], "itd5") == 0) ee_itd[5] = LeafBitMap[i];
90  if (strcmp(LeafNames[i], "itd6") == 0) ee_itd[6] = LeafBitMap[i];
91  if (strcmp(LeafNames[i], "itd7") == 0) ee_itd[7] = LeafBitMap[i];
92  if (strcmp(LeafNames[i], "itd8") == 0) ee_itd[8] = LeafBitMap[i];
93  if (strcmp(LeafNames[i], "itd9") == 0) ee_itd[9] = LeafBitMap[i];
94  }
95 
96 
97  if (_debugLevel > 9) printf("TRGGDLSummaryModule::initialize() end\n");
98 }
99 
100 void TRGGDLSummaryModule::event()
101 {
102 
103  if (_debugLevel > 9) printf("TRGGDLSummaryModule::event() start\n");
104 
105  int n_leafs = 0;
106  n_leafs = m_unpacker->getnLeafs();
107  int n_leafsExtra = 0;
108  n_leafsExtra = m_unpacker->getnLeafsExtra();
109  int n_clocks = m_unpacker->getnClks();
110  int nconf = m_unpacker->getconf();
111  int nword_input = m_unpacker->get_nword_input();
112  int nword_output = m_unpacker->get_nword_output();
113 
114  if (_debugLevel > 89)
115  printf("trggdlSummaryModule:n_leafs(%d), n_leafsExtra(%d), n_clocks(%d), nconf(%d), nword_input(%d), nword_output(%d)\n",
116  n_leafs, n_leafsExtra, n_clocks, nconf, nword_input, nword_output);
117 
118  StoreArray<TRGGDLUnpackerStore> entAry;
119  if (!entAry || !entAry.getEntries()) return;
120 
121  //prepare entAry adress
122  int clk_map = 0;
123  for (int i = 0; i < 320; i++) {
124  if (strcmp(entAry[0]->m_unpackername[i], "clk") == 0) clk_map = i;
125  }
126  if (_debugLevel > 89)
127  printf("trggdlSummaryModule:clk_map(%d)\n", clk_map);
128 
129  std::vector<std::vector<int> > _data(n_leafs + n_leafsExtra);
130  for (int leaf = 0; leaf < n_leafs + n_leafsExtra; leaf++) {
131  std::vector<int> _v(n_clocks);
132  _data[leaf] = _v;
133  }
134 
135  // fill "bit vs clk" for the event
136  for (int ii = 0; ii < entAry.getEntries(); ii++) {
137  if (_debugLevel > 89)
138  printf("trggdlSummaryModule:a:ii(%d)\n", ii);
139  std::vector<int*> Bits(n_leafs + n_leafsExtra);
140  //set pointer
141  for (int i = 0; i < 320; i++) {
142  if (LeafBitMap[i] != -1) {
143  Bits[LeafBitMap[i]] = &(entAry[ii]->m_unpacker[i]);
144  if (_debugLevel > 89)
145  printf("trggdlSummaryModule:ab:i(%d), LeafBitMap[i](%d), *Bits[LeafBitMap[i]](%d)\n",
146  i, LeafBitMap[i], *Bits[LeafBitMap[i]]);
147  } else {
148  if (_debugLevel > 89)
149  printf("trggdlSummaryModule:ab:i(%d), LeafBitMap[i](%d)\n",
150  i, LeafBitMap[i]);
151  }
152  }
153  for (int leaf = 0; leaf < n_leafs + n_leafsExtra; leaf++) {
154  if (_debugLevel > 89)
155  printf("trggdlSummaryModule:ad:leaf(%d),ii(%d),clk_map(%d),*Bits[leaf](%d), entAry[ii]->m_unpacker[clk_map](%d)\n",
156  leaf, ii, clk_map, *Bits[leaf], entAry[ii]->m_unpacker[clk_map]);
157  _data[leaf][entAry[ii]->m_unpacker[clk_map]] = *Bits[leaf];
158  }
159  }
160 
161  GDLResult.create(true);
162 
163  unsigned ored = 0;
164 
165  for (int j = 0; j < (int)nword_input; j++) {
166  if (_debugLevel > 89) printf("b:j(%d),", j);
167  ored = 0;
168  for (int clk = 0; clk < n_clocks; clk++) {
169  if (_debugLevel > 89) printf("clk(%d),", clk);
170  ored |= _data[ee_itd[j]][clk];
171  }
172  GDLResult->setInputBits(j, ored);
173  if (_debugLevel > 89) printf("\n");
174  }
175 
176  if (nconf == 0) {
177  ored = 0;
178  for (int clk = 0; clk < n_clocks; clk++) {
179  ored |= _data[ee_ftd[0]][clk];
180  }
181  GDLResult->setFtdlBits(0, ored);
182 
183  ored = 0;
184  for (int clk = 0; clk < n_clocks; clk++) {
185  ored |= (_data[ee_ftd[2]][clk] << 16) + _data[ee_ftd[1]][clk];
186  }
187  GDLResult->setFtdlBits(1, ored);
188 
189  ored = 0;
190  for (int clk = 0; clk < n_clocks; clk++) {
191  ored |= _data[ee_psn[0]][clk];
192  }
193  GDLResult->setPsnmBits(0, ored);
194 
195  ored = 0;
196  for (int clk = 0; clk < n_clocks; clk++) {
197  ored |= (_data[ee_psn[2]][clk] << 16) + _data[ee_psn[1]][clk];
198  }
199  GDLResult->setPsnmBits(1, ored);
200  } else {
201  for (int j = 0; j < (int)nword_output; j++) {
202  ored = 0;
203  for (int clk = 0; clk < n_clocks; clk++) {
204  ored |= _data[ee_ftd[j]][clk];
205  }
206  GDLResult->setFtdlBits(j, ored);
207  }
208 
209  for (int j = 0; j < (int)nword_output; j++) {
210  ored = 0;
211  for (int clk = 0; clk < n_clocks; clk++) {
212  ored |= _data[ee_psn[j]][clk];
213  }
214  GDLResult->setPsnmBits(j, ored);
215  }
216  }
217 
218  // reg_tmdl_timtype in header. 3bit, no quality info.
219  GDL::EGDLTimingType gtt = (GDL::EGDLTimingType)_data[_e_timtype][0];
220 
221  //get prescales
222  for (int i = 0; i < 320; i++) {
223  int bit1 = i / 32;
224  int bit2 = i % 32;
225  GDLResult->setPreScale(bit1, bit2, m_prescales->getprescales(i));
226  }
227 
228  TRGSummary::ETimingType tt = TRGSummary::TTYP_NONE;
229  if (gtt == GDL::e_tt_cdc) {
230  tt = TRGSummary::TTYP_CDC;
231  } else if (gtt == GDL::e_tt_ecl) {
232  tt = TRGSummary::TTYP_ECL;
233  } else if (gtt == GDL::e_tt_top) {
234  tt = TRGSummary::TTYP_TOP;
235  } else if (gtt == GDL::e_tt_dphy) {
236  tt = TRGSummary::TTYP_DPHY;
237  } else if (gtt == GDL::e_tt_rand) {
238  tt = TRGSummary::TTYP_RAND;
239  } else if (gtt == GDL::e_tt_psnm) {
240  tt = TRGSummary::TTYP_SELF;
241  } else {
242  tt = TRGSummary::TTYP_NONE;
243  }
244 
245  StoreObjPtr<EventMetaData> bevt;
246  unsigned _exp = bevt->getExperiment();
247  unsigned _run = bevt->getRun();
248  unsigned exprun = _exp * 1000000 + _run;
249  if (exprun < 13000500) {
250  GDLResult->setTimQuality(TRGSummary::TTYQ_CORS); // coarse
251  } else {
252  int rvcout = _data[_e_rvcout][0];
253  int q = (rvcout >> 1) & 3;
254  TRGSummary::ETimingQuality timQuality = TRGSummary::TTYQ_NONE;
255  switch (q) {
256  case 1:
257  timQuality = TRGSummary::TTYQ_CORS;
258  break;
259  case 2:
260  timQuality = TRGSummary::TTYQ_FINE;
261  break;
262  case 3:
263  timQuality = TRGSummary::TTYQ_SFIN;
264  break;
265  default:
266  timQuality = TRGSummary::TTYQ_NONE;
267  break;
268  }
269  GDLResult->setTimQuality(timQuality);
270  }
271 
272  if (exprun > 16000271) {
273  if (tt == TRGSummary::TTYP_RAND) {
274  int i_poissonin = GDLResult->getInputBitNumber(std::string("poissonin"));
275  int j_poissonin = i_poissonin / TRGSummary::c_trgWordSize;
276  int k_poissonin = i_poissonin % TRGSummary::c_trgWordSize;
277  int i_veto = GDLResult->getInputBitNumber(std::string("veto"));
278  int j_veto = i_veto / TRGSummary::c_trgWordSize;
279  int k_veto = i_veto % TRGSummary::c_trgWordSize;
280  for (int clk = 5; clk < n_clocks - 5; clk++) {
281  if ((1 << k_poissonin) & _data[ee_itd[j_poissonin]][clk]) {
282  tt = TRGSummary::TTYP_POIS;
283  if ((1 << k_veto) & _data[ee_itd[j_veto]][clk]) {
284  GDLResult->setPoissonInInjectionVeto();
285  }
286  }
287  }
288  }
289  }
290  GDLResult->setTimType(tt);
291 
292 }
Belle2::TRGSummary::TTYP_DPHY
@ TTYP_DPHY
delayed physics events for background
Definition: TRGSummary.h:76
Belle2::Module::setDescription
void setDescription(const std::string &description)
Sets the description of the module.
Definition: Module.cc:216
Belle2::TRGGDLSummaryModule::initialize
virtual void initialize() override
initialize
Definition: trggdlSummaryModule.cc:41
Belle2::TRGSummary::TTYP_CDC
@ TTYP_CDC
events triggered by CDC timing
Definition: TRGSummary.h:74
REG_MODULE
#define REG_MODULE(moduleName)
Register the given module (without 'Module' suffix) with the framework.
Definition: Module.h:652
Belle2::Module::c_ParallelProcessingCertified
@ c_ParallelProcessingCertified
This module can be run in parallel processing mode safely (All I/O must be done through the data stor...
Definition: Module.h:82
Belle2::TRGGDLSummaryModule::GDLResult
StoreObjPtr< TRGSummary > GDLResult
output for TRGSummary
Definition: trggdlSummaryModule.h:41
Belle2::TRGGDLSummaryModule::TRGGDLSummaryModule
TRGGDLSummaryModule()
Costructor.
Definition: trggdlSummaryModule.cc:31
Belle2::TRGSummary::TTYP_RAND
@ TTYP_RAND
random trigger events
Definition: TRGSummary.h:78
Belle2::TRGSummary::ETimingQuality
ETimingQuality
trigger timing type quality
Definition: TRGSummary.h:90
Belle2::TRGSummary::TTYP_ECL
@ TTYP_ECL
events triggered by ECL timing
Definition: TRGSummary.h:56
Belle2::TRGGDLSummaryModule::event
virtual void event() override
Event.
Definition: trggdlSummaryModule.cc:100
Belle2::TRGSummary::TTYP_SELF
@ TTYP_SELF
events triggered by self trigger
Definition: TRGSummary.h:64
Belle2::Module
Base class for Modules.
Definition: Module.h:74
Belle2::TRGGDLSummaryModule::_debugLevel
int _debugLevel
Debug Level.
Definition: trggdlSummaryModule.h:56
Belle2::Module::setPropertyFlags
void setPropertyFlags(unsigned int propertyFlags)
Sets the flags for the module properties.
Definition: Module.cc:210
Belle2::TRGSummary::TTYP_TOP
@ TTYP_TOP
events triggered by TOP timing
Definition: TRGSummary.h:72
Belle2
Abstract base class for different kinds of events.
Definition: MillepedeAlgorithm.h:19
Belle2::StoreObjPtr
Type-safe access to single objects in the data store.
Definition: ParticleList.h:33
Belle2::TRGSummary::c_trgWordSize
static const unsigned int c_trgWordSize
size of a l1 trigger word
Definition: TRGSummary.h:48
Belle2::Module::addParam
void addParam(const std::string &name, T &paramVariable, const std::string &description, const T &defaultValue)
Adds a new parameter to the module.
Definition: Module.h:562
Belle2::TRGSummary::ETimingType
ETimingType
types of trigger timing source defined in b2tt firmware
Definition: TRGSummary.h:54
Belle2::StoreArray
Accessor to arrays stored in the data store.
Definition: ECLMatchingPerformanceExpertModule.h:33
Belle2::TRGSummary::TTYP_NONE
@ TTYP_NONE
reserved (not defined yet)
Definition: TRGSummary.h:86
Belle2::StoreArray::getEntries
int getEntries() const
Get the number of objects in the array.
Definition: StoreArray.h:226
Belle2::TRGSummary::TTYP_POIS
@ TTYP_POIS
poisson random trigger
Definition: TRGSummary.h:84