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Belle II Software
release-05-02-19
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2 #include <framework/core/Module.h>
3 #include <cdc/dataobjects/CDCHit.h>
4 #include <framework/datastore/StoreArray.h>
5 #include <trg/cdc/dataobjects/Bitstream.h>
6 #include <trg/cdc/dataobjects/CDCTriggerSegmentHit.h>
7 #include <trg/cdc/Cosim.h>
14 #include <unordered_map>
25 namespace CDCTrigger {
26 enum class Priority : unsigned char {nothing, first, second};
28 std::unordered_map<unsigned, Priority> toPriorityMap = {{0, Priority::nothing},
29 {1, Priority::second},
30 {2, Priority::second},
33 Priority toPriority(
unsigned priorityPosition)
35 return toPriorityMap[priorityPosition];
37 enum MergerOut :
long unsigned int {priorityTime, fastestTime, edgeTime, hitmap, secondPriorityHit};
71 void event()
override;
77 static constexpr std::array<int, 9>
nMergers = {10, 10, 12, 14, 16, 18, 20, 22, 24};
80 static constexpr std::array<int, m_nSubModules>
nAxialMergers = {10, 12, 16, 20, 24};
131 using signalBus = std::array<outputArray, m_nSubModules>;
165 std::string
cwd = getcurrentdir();
183 std::array<pid_t, m_nSubModules>
m_pid;
213 std::array<streamPair, m_nSubModules>
stream;
227 void write(
const char* message, FILE* outstream);
253 template<
size_t nEdges>
255 std::array<timeVec, nSegmentsInMerger>,
256 std::array<timeVec, nSegmentsInMerger>,
257 std::array<timeVec, nEdges>,
258 std::array<std::bitset<nWiresInMerger>, 1>,
259 std::array<std::bitset<nSegmentsInMerger>, 1> >;
261 template<
size_t nEdges>
288 using TSMap = std::unordered_map<short, WireSet>;
293 using edgeMap = std::unordered_map<unsigned short, timeVec*>;
310 using edgeList = std::unordered_map<unsigned short, std::vector<unsigned short>>;
324 CDCTrigger::Priority
priority(
int index);
335 unsigned short trgTime(
int index,
int iFirstHit);
373 std::bitset<4>
timeStamp(
int index,
int iFirstHit);
406 template<CDCTrigger::MergerOut field,
size_t w
idth>
407 void pack(inputVector::reverse_iterator& rInput,
unsigned short mergerCellID(int index)
Get the cell ID in the merger.
std::vector< mergerVector > mergerOutput
Merger output.
static constexpr int clockPeriod
data clock period (32ns) in unit of 2ns
std::array< TSMap, 2 > m_tsMap
map from cell ID to TS ID, for inner and outer Merger
std::array< cellList, 3 > outerInvEdge
list of cell ID related to edge timing
std::tuple< std::array< timeVec, nSegmentsInMerger >, std::array< timeVec, nSegmentsInMerger >, std::array< timeVec, nEdges >, std::array< std::bitset< nWiresInMerger >, 1 >, std::array< std::bitset< nSegmentsInMerger >, 1 > > mergerStructElement
data structure to hold merger output <priority time (4 bits x 16), fast time (4 bits x 16),...
std::array< outputVector, nTrackers > outputArray
output array
static constexpr int width_out
width of output data width
void pack(inputVector::reverse_iterator &rInput, unsigned number, mergerStructElement< 5 > &output)
Pack the merger output data structure to TSF input vector.
std::array< outputArray, m_nSubModules > signalBus
signal bus
void terminate() override
close the pipes and wait for children to die.
std::string lib_extension
extension of lib
std::string wdbName_pre
wdb name prefix
std::string m_outputCollectionName
Name of the StoreArray holding the found TS hits.
CDCTrigger::Priority priority(int index)
write TSF input signals to the worker
Belle2::StoreArray< CDCHit > m_cdcHits
CDCHit array.
void write(const char *message, FILE *outstream)
write TSF input signals to the worker
static constexpr int nWiresInMerger
number of wire/cell in a single merger unit
StoreArray< signalBitStream > m_bitsTo2D
bitstream of TSF output to 2D tracker
Class to hold one clock cycle of raw bit content.
This class is the interface between TSim/Basf2 TSF module and the firmware simulation core of XSim/IS...
static constexpr int nCellsInLayer
Number of wire/cells in a single layer per merger unit.
unsigned short mergerNumber(int index)
Get the merger unit ID in a super layer.
bool notHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement ®)
Whether a time field in a merger has been hit in the clock cycle.
std::bitset< 4 > timeStamp(int index, int iFirstHit)
Get the trigger time stamp of a hit.
static constexpr int m_nClockPerEvent
how many clocks to simulate per event
char * getData(inputToTSFArray)
get the XSI compliant format from the bits format TSF input
priorityHitStruct m_priorityHit
list keeping the index of priority hit of a TS for making fastsim ts hit object
mergerOutArray outputFromMerger
bits format of merger output / TSF input
std::vector< inputVector > inputFromMerger
input array from Merger
std::array< std::array< int, 2 >, m_nSubModules > outputFileDescriptor
array holding file descriptors of pipes
bool m_allPositiveTime
switch If true, the trigger time of the hit with largest TDC count becomes 0.
std::string m_outputBitstreamNameTo2D
Name of the StoreArray holding the raw bit content to 2D trackers.
static constexpr int mergerWidth
merger output data width
std::vector< unsigned short > cellList
cell list
static constexpr std::array< int, 9 > nMergers
number of mergers in each super layer
void initialize() override
spawn child process for workers, open pipes to pass data
std::string m_hitCollectionName
Name of the StoreArray containing the input CDC hits.
std::map< unsigned, mergerStruct< 5 > > dataAcrossClocks
data structure to hold merger output
std::string simengine_libname
path to the simulation engine
bool m_mergerOnly
flag to only simulation merger and not TSF
WireSet segmentID(int iHit)
Get the list of associated track segments with a hit.
void simulateMerger(unsigned iclock)
Simulate 1 clock of merger.
void registerHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement ®)
Register the timing field so that later hits won't overwrite it.
static constexpr int nTrackers
number of trackers
std::array< char, mergerWidth > inputVector
input array
std::vector< mergerStructElement< nEdges > > mergerStruct
data structure to hold merger output
Abstract base class for different kinds of events.
std::array< streamPair, m_nSubModules > stream
array holding file handlers of pipes
std::map< unsigned, int > priorityHitInMerger
priority hits map in Merger
std::unordered_map< short, WireSet > TSMap
TS map.
std::array< mergerOutput, m_nSubModules > mergerOutArray
Merger output array.
static constexpr std::array< int, m_nSubModules > nAxialMergers
number of mergers in axial super layers
std::istream * ins
data stream
std::vector< std::vector< int > > iAxialHitInClock
CDC hit ID in each clock.
std::array< char, width_out > outputVector
output vector
std::string m_outputBitstreamNameToETF
Name of the StoreArray holding the raw bit content to ETF.
std::vector< bool > m_stubLUT
list of flags to run a TSF firmware simulation with dummy L/R LUT (to speed up loading)
std::string cwd
current diretory
static constexpr int nSegmentsInMerger
number of track segments in a single merger unit
inputToTSFArray inputToTSF
XSI compliant format of input to TSF.
void saveFastOutput(short iclock)
save fast TSIM output
std::map< unsigned, priorityHitStructInSL > priorityHitStructInClock
priority hits map in Merger for a clock
bool m_simulateCC
flag to simulate front-end clock counter
std::array< priorityHitStructInClock, m_nClockPerEvent > priorityHitStruct
all priority hits map in Merger
void saveFirmwareOutput()
save firmware output
void event() override
Things to do for each event.
int m_TDCCountForT0
TDC count value from T0.
std::string design_libname_pre
path to the simulation snapshot
std::bitset< timeWidth > timeVec
element of data structure to hold merger output
void computeEdges()
Compute the map from merger cell ID to all its related edge fields.
std::vector< short > WireSet
Wire set.
std::array< outputArray, m_nSubModules > outputToTracker
array holding TSF output data
std::array< edgeList, 2 > m_edge
map from cell ID to related edge ID
std::array< pid_t, m_nSubModules > m_pid
'1' in XSI VHDL simulation
std::array< std::bitset< nCellsInLayer >, 3 > registeredStructElement
record when a time slow has been registered by a hit <priority time, fast time, edge timing>
std::array< cellList, 5 > innerInvEdge
list of cell ID related to edge timing
std::string design_libname_post
path to the simulation snapshot
int m_debugLevel
debug level specified in the steering file
std::unordered_map< unsigned short, std::vector< unsigned short > > edgeList
edge wire list
CDCTriggerTSFFirmwareModule()
Constructor.
std::bitset< mergerWidth > mergerVector
Merger vector.
StoreArray< CDCTriggerSegmentHit > m_tsHits
unpacked track segment hit
std::array< inputFromMerger, m_nSubModules > inputToTSFArray
input array to TSF
int m_iFirstHit
ID of the earlist CDC hit in an event.
Accessor to arrays stored in the data store.
outputArray read(FILE *instream)
write TSF output signals from the worker
std::vector< priorityHitInMerger > priorityHitStructInSL
priority hits map in Merger for a SL
std::unordered_map< unsigned short, timeVec * > edgeMap
edge wire list
std::array< std::array< int, 2 >, m_nSubModules > inputFileDescriptor
array holding file descriptors of pipes
void setSecondPriority(unsigned priTS, unsigned iHit, timeVec hitTime, unsigned lr, mergerStructElement< 5 > &mergerData, registeredStructElement ®isteredCell, priorityHitInMerger &priorityHit)
set 2nd priority info
void initializeMerger()
Get CDC hits from the DataStore and distribute them to clocks.
std::string wdbName_post
wdb name extension
std::array< FILE *, 2 > streamPair
file handlers of pipes
static constexpr int m_nSubModules
number of TSF to simulate
unsigned short trgTime(int index, int iFirstHit)
Get the trigger time of the CDC hit.
static constexpr size_t timeWidth
bit width for priority time and fast time
std::vector< registeredStructElement > registeredStruct
vector of registeredStructElement