Belle II Software  release-05-02-19
CDCTriggerTSFFirmwareModule.h
1 #pragma once
2 #include <framework/core/Module.h>
3 #include <cdc/dataobjects/CDCHit.h>
4 #include <framework/datastore/StoreArray.h>
5 #include <trg/cdc/dataobjects/Bitstream.h>
6 #include <trg/cdc/dataobjects/CDCTriggerSegmentHit.h>
7 #include <trg/cdc/Cosim.h>
8 
9 #include <string>
10 #include <vector>
11 #include <bitset>
12 #include <array>
13 #include <tuple>
14 #include <unordered_map>
15 
16 #include <unistd.h>
17 #include <cstdio>
18 
19 namespace Belle2 {
25  namespace CDCTrigger {
26  enum class Priority : unsigned char {nothing, first, second};
28  std::unordered_map<unsigned, Priority> toPriorityMap = {{0, Priority::nothing},
29  {1, Priority::second},
30  {2, Priority::second},
31  {3, Priority::first}
32  };
33  Priority toPriority(unsigned priorityPosition)
34  {
35  return toPriorityMap[priorityPosition];
36  }
37  enum MergerOut : long unsigned int {priorityTime, fastestTime, edgeTime, hitmap, secondPriorityHit};
38  }
39 
49  public:
52 
53  virtual ~CDCTriggerTSFFirmwareModule();
54 
58  void initialize() override;
59 
63  void terminate() override;
64 
71  void event() override;
72 
74  static constexpr int m_nSubModules = 5;
75 
77  static constexpr std::array<int, 9> nMergers = {10, 10, 12, 14, 16, 18, 20, 22, 24};
78 
80  static constexpr std::array<int, m_nSubModules> nAxialMergers = {10, 12, 16, 20, 24};
81 
83  static constexpr int nTrackers = 4;
84 
86  static constexpr int mergerWidth = 256;
87 
89  static constexpr int width_out = 429;
90 
92  static constexpr int nWiresInMerger = 80;
93 
95  static constexpr int nCellsInLayer = 16;
96 
98  static constexpr int nSegmentsInMerger = 16;
99 
101  static constexpr size_t timeWidth = 4;
102 
104  static constexpr int m_nClockPerEvent = 44;
105 
107  static constexpr int clockPeriod = 16;
108 
109  protected:
111  std::string m_hitCollectionName;
112 
115 
118 
121 
124 
126  using outputVector = std::array<char, width_out>;
128  using outputArray = std::array<outputVector, nTrackers>;
129 
131  using signalBus = std::array<outputArray, m_nSubModules>;
134 
137 
140 
143 
146 
148  std::vector<bool> m_stubLUT;
149 
152 
154  int m_TDCCountForT0 = 4988;
155 
160  bool m_allPositiveTime = true;
161 
163  std::string lib_extension = ".so";
165  std::string cwd = getcurrentdir();
167  std::string design_libname_pre = cwd + "/xsim.dir/tsf";
169  std::string design_libname_post = "/xsimk" + lib_extension;
171  std::string simengine_libname = "librdi_simulator_kernel" + lib_extension;
173  std::string wdbName_pre = "tsf";
175  std::string wdbName_post = ".wdb";
176 
178  /* static constexpr char one_val = 3; */
180  /* static constexpr char zero_val = 2; */
181 
183  std::array<pid_t, m_nSubModules> m_pid;
184 
186  using mergerVector = std::bitset<mergerWidth>;
188  using mergerOutput = std::vector<mergerVector>;
190  using mergerOutArray = std::array<mergerOutput, m_nSubModules>;
193 
195  using inputVector = std::array<char, mergerWidth>;
197  using inputFromMerger = std::vector<inputVector>;
199  using inputToTSFArray = std::array<inputFromMerger, m_nSubModules>;
202 
204  std::array<outputArray, m_nSubModules> outputToTracker;
205 
207  template<int iSL>
208  char* getData(inputToTSFArray);
209 
211  using streamPair = std::array<FILE*, 2>;
213  std::array<streamPair, m_nSubModules> stream;
214 
216  std::array<std::array<int, 2>, m_nSubModules> inputFileDescriptor;
218  std::array<std::array<int, 2>, m_nSubModules> outputFileDescriptor;
219 
227  void write(const char* message, FILE* outstream);
228 
236  outputArray read(FILE* instream);
237 
239  std::istream* ins;
240 
241  /**************************************************
242  * Merger simulation
243  **************************************************/
244 
246  using timeVec = std::bitset<timeWidth>;
253  template<size_t nEdges>
254  using mergerStructElement = std::tuple <
255  std::array<timeVec, nSegmentsInMerger>,
256  std::array<timeVec, nSegmentsInMerger>,
257  std::array<timeVec, nEdges>,
258  std::array<std::bitset<nWiresInMerger>, 1>,
259  std::array<std::bitset<nSegmentsInMerger>, 1> >;
261  template<size_t nEdges>
262  using mergerStruct = std::vector<mergerStructElement<nEdges> >;
264  std::map<unsigned, mergerStruct<5> > dataAcrossClocks;
265 
268  using registeredStructElement = std::array<std::bitset<nCellsInLayer>, 3>;
270  using registeredStruct = std::vector<registeredStructElement>;
271 
273  using priorityHitInMerger = std::map<unsigned, int>;
275  using priorityHitStructInSL = std::vector<priorityHitInMerger>;
277  using priorityHitStructInClock = std::map<unsigned, priorityHitStructInSL>;
279  using priorityHitStruct = std::array<priorityHitStructInClock, m_nClockPerEvent>;
283  std::vector<std::vector<int> > iAxialHitInClock;
284 
286  using WireSet = std::vector<short>;
288  using TSMap = std::unordered_map<short, WireSet>;
290  std::array<TSMap, 2> m_tsMap;
291 
293  using edgeMap = std::unordered_map<unsigned short, timeVec*>;
295  using cellList = std::vector<unsigned short>;
297  std::array<cellList, 5> innerInvEdge = {cellList {31},
298  cellList {64},
299  cellList {32, 48, 64, 65},
300  cellList {31, 47, 62, 63, 78},
301  cellList {63, 79}
302  };
303 
305  std::array<cellList, 3> outerInvEdge = {cellList {63},
306  cellList {0, 64},
307  cellList {15, 31, 63, 79}
308  };
310  using edgeList = std::unordered_map<unsigned short, std::vector<unsigned short>>;
312  std::array<edgeList, 2> m_edge;
313 
316 
324  CDCTrigger::Priority priority(int index);
325 
335  unsigned short trgTime(int index, int iFirstHit);
336 
344  unsigned short mergerCellID(int index);
345 
353  unsigned short mergerNumber(int index);
354 
362  WireSet segmentID(int iHit);
363 
373  std::bitset<4> timeStamp(int index, int iFirstHit);
374 
378  void computeEdges();
379 
384  void initializeMerger();
385 
391  void simulateMerger(unsigned iclock);
392 
406  template<CDCTrigger::MergerOut field, size_t width>
407  void pack(inputVector::reverse_iterator& rInput,
408  unsigned number, mergerStructElement<5>& output);
409 
421  bool notHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement& reg);
422 
432  void registerHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement& reg);
433 
435  void saveFirmwareOutput();
436 
438  void saveFastOutput(short iclock);
439 
441  void setSecondPriority(unsigned priTS,
442  unsigned iHit,
443  timeVec hitTime,
444  unsigned lr,
445  mergerStructElement<5>& mergerData,
446  registeredStructElement& registeredCell,
447  priorityHitInMerger& priorityHit);
448  };
450 }
Belle2::CDCTriggerTSFFirmwareModule::mergerCellID
unsigned short mergerCellID(int index)
Get the cell ID in the merger.
Definition: CDCTriggerTSFFirmwareModule.cc:237
Belle2::CDCTriggerTSFFirmwareModule::mergerOutput
std::vector< mergerVector > mergerOutput
Merger output.
Definition: CDCTriggerTSFFirmwareModule.h:188
Belle2::CDCTriggerTSFFirmwareModule::clockPeriod
static constexpr int clockPeriod
data clock period (32ns) in unit of 2ns
Definition: CDCTriggerTSFFirmwareModule.h:107
Belle2::CDCTriggerTSFFirmwareModule::m_tsMap
std::array< TSMap, 2 > m_tsMap
map from cell ID to TS ID, for inner and outer Merger
Definition: CDCTriggerTSFFirmwareModule.h:290
Belle2::CDCTriggerTSFFirmwareModule::outerInvEdge
std::array< cellList, 3 > outerInvEdge
list of cell ID related to edge timing
Definition: CDCTriggerTSFFirmwareModule.h:305
Belle2::CDCTriggerTSFFirmwareModule::mergerStructElement
std::tuple< std::array< timeVec, nSegmentsInMerger >, std::array< timeVec, nSegmentsInMerger >, std::array< timeVec, nEdges >, std::array< std::bitset< nWiresInMerger >, 1 >, std::array< std::bitset< nSegmentsInMerger >, 1 > > mergerStructElement
data structure to hold merger output <priority time (4 bits x 16), fast time (4 bits x 16),...
Definition: CDCTriggerTSFFirmwareModule.h:259
Belle2::CDCTriggerTSFFirmwareModule::outputArray
std::array< outputVector, nTrackers > outputArray
output array
Definition: CDCTriggerTSFFirmwareModule.h:128
Belle2::CDCTriggerTSFFirmwareModule::width_out
static constexpr int width_out
width of output data width
Definition: CDCTriggerTSFFirmwareModule.h:89
Belle2::CDCTriggerTSFFirmwareModule::pack
void pack(inputVector::reverse_iterator &rInput, unsigned number, mergerStructElement< 5 > &output)
Pack the merger output data structure to TSF input vector.
Definition: CDCTriggerTSFFirmwareModule.cc:520
Belle2::CDCTriggerTSFFirmwareModule::signalBus
std::array< outputArray, m_nSubModules > signalBus
signal bus
Definition: CDCTriggerTSFFirmwareModule.h:131
Belle2::CDCTriggerTSFFirmwareModule::terminate
void terminate() override
close the pipes and wait for children to die.
Definition: CDCTriggerTSFFirmwareModule.cc:181
Belle2::CDCTriggerTSFFirmwareModule::lib_extension
std::string lib_extension
extension of lib
Definition: CDCTriggerTSFFirmwareModule.h:163
Belle2::CDCTriggerTSFFirmwareModule::wdbName_pre
std::string wdbName_pre
wdb name prefix
Definition: CDCTriggerTSFFirmwareModule.h:173
Belle2::CDCTriggerTSFFirmwareModule::m_outputCollectionName
std::string m_outputCollectionName
Name of the StoreArray holding the found TS hits.
Definition: CDCTriggerTSFFirmwareModule.h:114
Belle2::CDCTriggerTSFFirmwareModule::priority
CDCTrigger::Priority priority(int index)
write TSF input signals to the worker
Definition: CDCTriggerTSFFirmwareModule.cc:81
Belle2::CDCTriggerTSFFirmwareModule::m_cdcHits
Belle2::StoreArray< CDCHit > m_cdcHits
CDCHit array.
Definition: CDCTriggerTSFFirmwareModule.h:123
Belle2::CDCTriggerTSFFirmwareModule::write
void write(const char *message, FILE *outstream)
write TSF input signals to the worker
Definition: CDCTriggerTSFFirmwareModule.cc:92
Belle2::CDCTriggerTSFFirmwareModule::nWiresInMerger
static constexpr int nWiresInMerger
number of wire/cell in a single merger unit
Definition: CDCTriggerTSFFirmwareModule.h:92
Belle2::CDCTriggerTSFFirmwareModule::m_bitsTo2D
StoreArray< signalBitStream > m_bitsTo2D
bitstream of TSF output to 2D tracker
Definition: CDCTriggerTSFFirmwareModule.h:136
Belle2::Bitstream
Class to hold one clock cycle of raw bit content.
Definition: Bitstream.h:47
Belle2::CDCTriggerTSFFirmwareModule
This class is the interface between TSim/Basf2 TSF module and the firmware simulation core of XSim/IS...
Definition: CDCTriggerTSFFirmwareModule.h:48
Belle2::CDCTriggerTSFFirmwareModule::nCellsInLayer
static constexpr int nCellsInLayer
Number of wire/cells in a single layer per merger unit.
Definition: CDCTriggerTSFFirmwareModule.h:95
Belle2::CDCTriggerTSFFirmwareModule::mergerNumber
unsigned short mergerNumber(int index)
Get the merger unit ID in a super layer.
Definition: CDCTriggerTSFFirmwareModule.cc:245
Belle2::CDCTriggerTSFFirmwareModule::notHit
bool notHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement &reg)
Whether a time field in a merger has been hit in the clock cycle.
Belle2::CDCTriggerTSFFirmwareModule::timeStamp
std::bitset< 4 > timeStamp(int index, int iFirstHit)
Get the trigger time stamp of a hit.
Definition: CDCTriggerTSFFirmwareModule.cc:232
Belle2::CDCTriggerTSFFirmwareModule::m_nClockPerEvent
static constexpr int m_nClockPerEvent
how many clocks to simulate per event
Definition: CDCTriggerTSFFirmwareModule.h:104
Belle2::CDCTriggerTSFFirmwareModule::getData
char * getData(inputToTSFArray)
get the XSI compliant format from the bits format TSF input
Definition: CDCTriggerTSFFirmwareModule.cc:209
Belle2::CDCTriggerTSFFirmwareModule::m_priorityHit
priorityHitStruct m_priorityHit
list keeping the index of priority hit of a TS for making fastsim ts hit object
Definition: CDCTriggerTSFFirmwareModule.h:281
Belle2::CDCTriggerTSFFirmwareModule::outputFromMerger
mergerOutArray outputFromMerger
bits format of merger output / TSF input
Definition: CDCTriggerTSFFirmwareModule.h:192
Belle2::CDCTriggerTSFFirmwareModule::inputFromMerger
std::vector< inputVector > inputFromMerger
input array from Merger
Definition: CDCTriggerTSFFirmwareModule.h:197
Belle2::CDCTriggerTSFFirmwareModule::outputFileDescriptor
std::array< std::array< int, 2 >, m_nSubModules > outputFileDescriptor
array holding file descriptors of pipes
Definition: CDCTriggerTSFFirmwareModule.h:218
Belle2::CDCTriggerTSFFirmwareModule::m_allPositiveTime
bool m_allPositiveTime
switch If true, the trigger time of the hit with largest TDC count becomes 0.
Definition: CDCTriggerTSFFirmwareModule.h:160
Belle2::CDCTriggerTSFFirmwareModule::m_outputBitstreamNameTo2D
std::string m_outputBitstreamNameTo2D
Name of the StoreArray holding the raw bit content to 2D trackers.
Definition: CDCTriggerTSFFirmwareModule.h:117
Belle2::CDCTriggerTSFFirmwareModule::mergerWidth
static constexpr int mergerWidth
merger output data width
Definition: CDCTriggerTSFFirmwareModule.h:86
Belle2::CDCTriggerTSFFirmwareModule::cellList
std::vector< unsigned short > cellList
cell list
Definition: CDCTriggerTSFFirmwareModule.h:295
Belle2::CDCTriggerTSFFirmwareModule::nMergers
static constexpr std::array< int, 9 > nMergers
number of mergers in each super layer
Definition: CDCTriggerTSFFirmwareModule.h:77
Belle2::CDCTriggerTSFFirmwareModule::initialize
void initialize() override
spawn child process for workers, open pipes to pass data
Definition: CDCTriggerTSFFirmwareModule.cc:122
Belle2::CDCTriggerTSFFirmwareModule::m_hitCollectionName
std::string m_hitCollectionName
Name of the StoreArray containing the input CDC hits.
Definition: CDCTriggerTSFFirmwareModule.h:111
Belle2::CDCTriggerTSFFirmwareModule::dataAcrossClocks
std::map< unsigned, mergerStruct< 5 > > dataAcrossClocks
data structure to hold merger output
Definition: CDCTriggerTSFFirmwareModule.h:264
Belle2::CDCTriggerTSFFirmwareModule::simengine_libname
std::string simengine_libname
path to the simulation engine
Definition: CDCTriggerTSFFirmwareModule.h:171
Belle2::Module
Base class for Modules.
Definition: Module.h:74
Belle2::CDCTriggerTSFFirmwareModule::m_mergerOnly
bool m_mergerOnly
flag to only simulation merger and not TSF
Definition: CDCTriggerTSFFirmwareModule.h:142
Belle2::CDCTriggerTSFFirmwareModule::segmentID
WireSet segmentID(int iHit)
Get the list of associated track segments with a hit.
Definition: CDCTriggerTSFFirmwareModule.cc:254
Belle2::CDCTriggerTSFFirmwareModule::simulateMerger
void simulateMerger(unsigned iclock)
Simulate 1 clock of merger.
Definition: CDCTriggerTSFFirmwareModule.cc:366
Belle2::CDCTriggerTSFFirmwareModule::registerHit
void registerHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement &reg)
Register the timing field so that later hits won't overwrite it.
Belle2::CDCTriggerTSFFirmwareModule::nTrackers
static constexpr int nTrackers
number of trackers
Definition: CDCTriggerTSFFirmwareModule.h:83
Belle2::CDCTriggerTSFFirmwareModule::inputVector
std::array< char, mergerWidth > inputVector
input array
Definition: CDCTriggerTSFFirmwareModule.h:195
Belle2::CDCTriggerTSFFirmwareModule::mergerStruct
std::vector< mergerStructElement< nEdges > > mergerStruct
data structure to hold merger output
Definition: CDCTriggerTSFFirmwareModule.h:262
Belle2
Abstract base class for different kinds of events.
Definition: MillepedeAlgorithm.h:19
Belle2::CDCTriggerTSFFirmwareModule::stream
std::array< streamPair, m_nSubModules > stream
array holding file handlers of pipes
Definition: CDCTriggerTSFFirmwareModule.h:213
Belle2::CDCTriggerTSFFirmwareModule::priorityHitInMerger
std::map< unsigned, int > priorityHitInMerger
priority hits map in Merger
Definition: CDCTriggerTSFFirmwareModule.h:273
Belle2::CDCTriggerTSFFirmwareModule::TSMap
std::unordered_map< short, WireSet > TSMap
TS map.
Definition: CDCTriggerTSFFirmwareModule.h:288
Belle2::CDCTriggerTSFFirmwareModule::mergerOutArray
std::array< mergerOutput, m_nSubModules > mergerOutArray
Merger output array.
Definition: CDCTriggerTSFFirmwareModule.h:190
Belle2::CDCTriggerTSFFirmwareModule::nAxialMergers
static constexpr std::array< int, m_nSubModules > nAxialMergers
number of mergers in axial super layers
Definition: CDCTriggerTSFFirmwareModule.h:80
Belle2::CDCTriggerTSFFirmwareModule::ins
std::istream * ins
data stream
Definition: CDCTriggerTSFFirmwareModule.h:239
Belle2::CDCTriggerTSFFirmwareModule::iAxialHitInClock
std::vector< std::vector< int > > iAxialHitInClock
CDC hit ID in each clock.
Definition: CDCTriggerTSFFirmwareModule.h:283
Belle2::CDCTriggerTSFFirmwareModule::outputVector
std::array< char, width_out > outputVector
output vector
Definition: CDCTriggerTSFFirmwareModule.h:126
Belle2::CDCTriggerTSFFirmwareModule::m_outputBitstreamNameToETF
std::string m_outputBitstreamNameToETF
Name of the StoreArray holding the raw bit content to ETF.
Definition: CDCTriggerTSFFirmwareModule.h:120
Belle2::CDCTriggerTSFFirmwareModule::m_stubLUT
std::vector< bool > m_stubLUT
list of flags to run a TSF firmware simulation with dummy L/R LUT (to speed up loading)
Definition: CDCTriggerTSFFirmwareModule.h:148
Belle2::CDCTriggerTSFFirmwareModule::cwd
std::string cwd
current diretory
Definition: CDCTriggerTSFFirmwareModule.h:165
Belle2::CDCTriggerTSFFirmwareModule::nSegmentsInMerger
static constexpr int nSegmentsInMerger
number of track segments in a single merger unit
Definition: CDCTriggerTSFFirmwareModule.h:98
Belle2::CDCTriggerTSFFirmwareModule::inputToTSF
inputToTSFArray inputToTSF
XSI compliant format of input to TSF.
Definition: CDCTriggerTSFFirmwareModule.h:201
Belle2::CDCTriggerTSFFirmwareModule::saveFastOutput
void saveFastOutput(short iclock)
save fast TSIM output
Definition: CDCTriggerTSFFirmwareModule.cc:540
Belle2::CDCTriggerTSFFirmwareModule::priorityHitStructInClock
std::map< unsigned, priorityHitStructInSL > priorityHitStructInClock
priority hits map in Merger for a clock
Definition: CDCTriggerTSFFirmwareModule.h:277
Belle2::CDCTriggerTSFFirmwareModule::m_simulateCC
bool m_simulateCC
flag to simulate front-end clock counter
Definition: CDCTriggerTSFFirmwareModule.h:145
Belle2::CDCTriggerTSFFirmwareModule::priorityHitStruct
std::array< priorityHitStructInClock, m_nClockPerEvent > priorityHitStruct
all priority hits map in Merger
Definition: CDCTriggerTSFFirmwareModule.h:279
Belle2::CDCTriggerTSFFirmwareModule::saveFirmwareOutput
void saveFirmwareOutput()
save firmware output
Definition: CDCTriggerTSFFirmwareModule.cc:533
Belle2::CDCTriggerTSFFirmwareModule::event
void event() override
Things to do for each event.
Definition: CDCTriggerTSFFirmwareModule.cc:647
Belle2::CDCTriggerTSFFirmwareModule::m_TDCCountForT0
int m_TDCCountForT0
TDC count value from T0.
Definition: CDCTriggerTSFFirmwareModule.h:154
Belle2::CDCTriggerTSFFirmwareModule::design_libname_pre
std::string design_libname_pre
path to the simulation snapshot
Definition: CDCTriggerTSFFirmwareModule.h:167
Belle2::CDCTriggerTSFFirmwareModule::timeVec
std::bitset< timeWidth > timeVec
element of data structure to hold merger output
Definition: CDCTriggerTSFFirmwareModule.h:246
Belle2::CDCTriggerTSFFirmwareModule::computeEdges
void computeEdges()
Compute the map from merger cell ID to all its related edge fields.
Definition: CDCTriggerTSFFirmwareModule.cc:194
Belle2::CDCTriggerTSFFirmwareModule::WireSet
std::vector< short > WireSet
Wire set.
Definition: CDCTriggerTSFFirmwareModule.h:286
Belle2::CDCTriggerTSFFirmwareModule::outputToTracker
std::array< outputArray, m_nSubModules > outputToTracker
array holding TSF output data
Definition: CDCTriggerTSFFirmwareModule.h:204
Belle2::CDCTriggerTSFFirmwareModule::m_edge
std::array< edgeList, 2 > m_edge
map from cell ID to related edge ID
Definition: CDCTriggerTSFFirmwareModule.h:312
Belle2::CDCTriggerTSFFirmwareModule::m_pid
std::array< pid_t, m_nSubModules > m_pid
'1' in XSI VHDL simulation
Definition: CDCTriggerTSFFirmwareModule.h:183
Belle2::CDCTriggerTSFFirmwareModule::registeredStructElement
std::array< std::bitset< nCellsInLayer >, 3 > registeredStructElement
record when a time slow has been registered by a hit <priority time, fast time, edge timing>
Definition: CDCTriggerTSFFirmwareModule.h:268
Belle2::CDCTriggerTSFFirmwareModule::innerInvEdge
std::array< cellList, 5 > innerInvEdge
list of cell ID related to edge timing
Definition: CDCTriggerTSFFirmwareModule.h:297
Belle2::CDCTriggerTSFFirmwareModule::design_libname_post
std::string design_libname_post
path to the simulation snapshot
Definition: CDCTriggerTSFFirmwareModule.h:169
Belle2::CDCTriggerTSFFirmwareModule::m_debugLevel
int m_debugLevel
debug level specified in the steering file
Definition: CDCTriggerTSFFirmwareModule.h:151
Belle2::CDCTriggerTSFFirmwareModule::edgeList
std::unordered_map< unsigned short, std::vector< unsigned short > > edgeList
edge wire list
Definition: CDCTriggerTSFFirmwareModule.h:310
Belle2::CDCTriggerTSFFirmwareModule::CDCTriggerTSFFirmwareModule
CDCTriggerTSFFirmwareModule()
Constructor.
Definition: CDCTriggerTSFFirmwareModule.cc:42
Belle2::CDCTriggerTSFFirmwareModule::mergerVector
std::bitset< mergerWidth > mergerVector
Merger vector.
Definition: CDCTriggerTSFFirmwareModule.h:186
Belle2::CDCTriggerTSFFirmwareModule::m_tsHits
StoreArray< CDCTriggerSegmentHit > m_tsHits
unpacked track segment hit
Definition: CDCTriggerTSFFirmwareModule.h:139
Belle2::CDCTriggerTSFFirmwareModule::inputToTSFArray
std::array< inputFromMerger, m_nSubModules > inputToTSFArray
input array to TSF
Definition: CDCTriggerTSFFirmwareModule.h:199
Belle2::CDCTriggerTSFFirmwareModule::m_iFirstHit
int m_iFirstHit
ID of the earlist CDC hit in an event.
Definition: CDCTriggerTSFFirmwareModule.h:315
Belle2::StoreArray
Accessor to arrays stored in the data store.
Definition: ECLMatchingPerformanceExpertModule.h:33
Belle2::CDCTriggerTSFFirmwareModule::read
outputArray read(FILE *instream)
write TSF output signals from the worker
Definition: CDCTriggerTSFFirmwareModule.cc:99
Belle2::CDCTriggerTSFFirmwareModule::priorityHitStructInSL
std::vector< priorityHitInMerger > priorityHitStructInSL
priority hits map in Merger for a SL
Definition: CDCTriggerTSFFirmwareModule.h:275
Belle2::CDCTriggerTSFFirmwareModule::edgeMap
std::unordered_map< unsigned short, timeVec * > edgeMap
edge wire list
Definition: CDCTriggerTSFFirmwareModule.h:293
Belle2::CDCTriggerTSFFirmwareModule::inputFileDescriptor
std::array< std::array< int, 2 >, m_nSubModules > inputFileDescriptor
array holding file descriptors of pipes
Definition: CDCTriggerTSFFirmwareModule.h:216
Belle2::CDCTriggerTSFFirmwareModule::setSecondPriority
void setSecondPriority(unsigned priTS, unsigned iHit, timeVec hitTime, unsigned lr, mergerStructElement< 5 > &mergerData, registeredStructElement &registeredCell, priorityHitInMerger &priorityHit)
set 2nd priority info
Definition: CDCTriggerTSFFirmwareModule.cc:343
Belle2::CDCTriggerTSFFirmwareModule::initializeMerger
void initializeMerger()
Get CDC hits from the DataStore and distribute them to clocks.
Definition: CDCTriggerTSFFirmwareModule.cc:278
Belle2::CDCTriggerTSFFirmwareModule::wdbName_post
std::string wdbName_post
wdb name extension
Definition: CDCTriggerTSFFirmwareModule.h:175
Belle2::CDCTriggerTSFFirmwareModule::streamPair
std::array< FILE *, 2 > streamPair
file handlers of pipes
Definition: CDCTriggerTSFFirmwareModule.h:211
Belle2::CDCTriggerTSFFirmwareModule::m_nSubModules
static constexpr int m_nSubModules
number of TSF to simulate
Definition: CDCTriggerTSFFirmwareModule.h:74
Belle2::CDCTriggerTSFFirmwareModule::trgTime
unsigned short trgTime(int index, int iFirstHit)
Get the trigger time of the CDC hit.
Definition: CDCTriggerTSFFirmwareModule.cc:222
Belle2::CDCTriggerTSFFirmwareModule::timeWidth
static constexpr size_t timeWidth
bit width for priority time and fast time
Definition: CDCTriggerTSFFirmwareModule.h:101
Belle2::CDCTriggerTSFFirmwareModule::registeredStruct
std::vector< registeredStructElement > registeredStruct
vector of registeredStructElement
Definition: CDCTriggerTSFFirmwareModule.h:270