Belle II Software  release-05-02-19
FrontEnd.h
1 //-----------------------------------------------------------------------------
2 // $Id$
3 //-----------------------------------------------------------------------------
4 // Filename : FrontEnd.h
5 // Section : TRG CDC
6 // Owner : Yoshihito Iwasaki
7 // Email : yoshihito.iwasaki@kek.jp
8 //-----------------------------------------------------------------------------
9 // Description : A class to represent a CDC front-end board
10 //-----------------------------------------------------------------------------
11 // $Log$
12 //-----------------------------------------------------------------------------
13 
14 #ifndef TRGCDCFrontEnd_FLAG_
15 #define TRGCDCFrontEnd_FLAG_
16 
17 #include <fstream>
18 #include <string>
19 #include "trg/trg/Board.h"
20 #include "trg/trg/SignalVector.h"
21 #include "trg/trg/SignalBundle.h"
22 
23 #ifdef TRGCDC_SHORT_NAMES
24 #define TCFrontEnd TRGCDCFrontEnd
25 #endif
26 
27 namespace Belle2 {
33  class TRGCDCWire;
34 
37  : public TRGBoard,
38  public std::vector<const TRGCDCWire*> {
39 
40  public:// enum
42  enum boardType {
43  innerInside = 0, // inner of the inner-most super layer
44  innerOutside = 1, // outer of the inner-most super layer
45  outerInside = 2, // inner of the ouer super layer
46  outerOutside = 3, // outer of the ouer super layer
47  unknown = 999
48  };
49 
50  public:
51 
53  TRGCDCFrontEnd(const std::string& name,
55  const TRGClock& systemClock,
56  const TRGClock& dataClock,
57  const TRGClock& userClock);
58 
60  virtual ~TRGCDCFrontEnd();
61 
62 
63  public:// Selectors
64 
66  static std::string version(void);
67 
69  boardType type(void) const;
70 
71  public:// Modifiers
72 
74  void simulate(void);
75 
77  // TRGSignalBundle output(void) { return *_osb;};
78  TRGSignalBundle* getOSB(void) const { return _osb; };
79 
80 
81  public:// VHDL utilities
82 
84  static TRGState packerInnerInside(const TRGState& input);
85 
87  static TRGState packerInnerOutside(const TRGState& input);
88 
90  static TRGState packerOuterInside(const TRGState& input);
91 
93  static TRGState packerOuterOutside(const TRGState& input);
94 
96  static void unpackerInnerInside(const TRGState& input,
97  const TRGState& output);
98 
100  static void unpackerInnerOutside(const TRGState& input,
101  const TRGState& output);
102 
104  static void unpackerOuterInside(const TRGState& input,
105  const TRGState& output);
106 
108  static void unpackerOuterOutside(const TRGState& input,
109  const TRGState& output);
110 
113  static int implementation(const boardType& type, std::ofstream&);
114 
116  static int implementationPort(const boardType& type, std::ofstream&);
117 
118  public:// Configuration
119 
121  void push_back(const TRGCDCWire*);
122 
125  void dump(const std::string& message = "",
126  const std::string& pre = "") const;
127 
129  void dump_log(void) const;
131  void dump_log_innerInside(void) const;
133  void dump_log_innerOutside(void) const;
135  void dump_log_outerInside(void) const;
137  void dump_log_outerOutside(void) const;
138 
139 // public: // allow Merger class to access FrontEnd data
140 
141  //friend class TRGCDCMerger;
142 
143  private:
144 
147 
150 
153  };
154 
155 //-----------------------------------------------------------------------------
156 
158 } // namespace Belle2
159 
160 #endif /* TRGCDCFrontEnd_FLAG_ */
Belle2::TRGBoard
A class to represent a trigger board.
Definition: Board.h:30
Belle2::TRGCDCFrontEnd::unpackerInnerInside
static void unpackerInnerInside(const TRGState &input, const TRGState &output)
Unpacks TRGState.
Belle2::TRGCDCFrontEnd::dump_log_innerOutside
void dump_log_innerOutside(void) const
Dump all the details of _mosb into a .log file, for innerOutside FE.
Definition: FrontEnd.cc:1669
Belle2::TRGCDCFrontEnd::implementationPort
static int implementationPort(const boardType &type, std::ofstream &)
writes a port map.
Definition: FrontEnd.cc:103
Belle2::TRGCDCFrontEnd::packerInnerInside
static TRGState packerInnerInside(const TRGState &input)
Makes bit pattern using input bit pattern for the inner FE.
Belle2::TRGCDCFrontEnd::_isb
TRGSignalBundle * _isb
Input signal bundle.
Definition: FrontEnd.h:149
Belle2::TRGCDCFrontEnd::dump_log_outerOutside
void dump_log_outerOutside(void) const
Dump all the details of _mosb into a .log file, for outerOutside FE.
Definition: FrontEnd.cc:1772
Belle2::TRGCDCFrontEnd::simulate
void simulate(void)
simulates firmware.
Definition: FrontEnd.cc:153
Belle2::TRGCDCFrontEnd::unpackerInnerOutside
static void unpackerInnerOutside(const TRGState &input, const TRGState &output)
Unpacks TRGState.
Belle2::TRGState
A class to represent a state of multi bits.
Definition: State.h:29
Belle2::TRGCDCWire
A class to represent a wire in CDC.
Definition: Wire.h:57
Belle2::TRGCDCFrontEnd
A class to represent a CDC front-end board.
Definition: FrontEnd.h:36
Belle2::TRGCDCFrontEnd::_osb
TRGSignalBundle * _osb
Output signal bundle.
Definition: FrontEnd.h:152
Belle2::TRGSignalBundle
A class to represent a bundle of SignalVectors.
Definition: SignalBundle.h:31
Belle2::TRGBoard::name
const std::string & name(void) const
returns name.
Definition: Board.h:114
Belle2::TRGCDCFrontEnd::dump_log
void dump_log(void) const
Dump all the details of _mosb into a .log file, do it in the end of simulate()
Definition: FrontEnd.cc:1601
Belle2::TRGCDCFrontEnd::_type
boardType _type
Board type.
Definition: FrontEnd.h:146
Belle2::TRGCDCFrontEnd::dump
void dump(const std::string &message="", const std::string &pre="") const
dumps contents.
Definition: FrontEnd.cc:147
Belle2::TRGCDCFrontEnd::packerOuterOutside
static TRGState packerOuterOutside(const TRGState &input)
Makes bit pattern using input bit pattern for the outer FE.
Belle2::TRGCDCFrontEnd::unpackerOuterInside
static void unpackerOuterInside(const TRGState &input, const TRGState &output)
Unpacks TRGState.
Belle2::TRGCDCFrontEnd::version
static std::string version(void)
returns version.
Definition: FrontEnd.cc:54
Belle2::TRGCDCFrontEnd::unpackerOuterOutside
static void unpackerOuterOutside(const TRGState &input, const TRGState &output)
Unpacks TRGState.
Belle2
Abstract base class for different kinds of events.
Definition: MillepedeAlgorithm.h:19
Belle2::TRGCDCFrontEnd::TRGCDCFrontEnd
TRGCDCFrontEnd(const std::string &name, boardType type, const TRGClock &systemClock, const TRGClock &dataClock, const TRGClock &userClock)
Constructor.
Definition: FrontEnd.cc:32
Belle2::TRGCDCFrontEnd::boardType
boardType
enum boardType
Definition: FrontEnd.h:42
Belle2::TRGCDCFrontEnd::type
boardType type(void) const
returns type.
Definition: FrontEnd.cc:60
Belle2::TRGCDCFrontEnd::packerOuterInside
static TRGState packerOuterInside(const TRGState &input)
Makes bit pattern using input bit pattern for the inner FE.
Belle2::TRGCDCFrontEnd::packerInnerOutside
static TRGState packerInnerOutside(const TRGState &input)
Makes bit pattern using input bit pattern for the outer FE.
Belle2::TRGCDCFrontEnd::dump_log_innerInside
void dump_log_innerInside(void) const
Dump all the details of _mosb into a .log file, for innerInside FE.
Definition: FrontEnd.cc:1612
Belle2::TRGCDCFrontEnd::push_back
void push_back(const TRGCDCWire *)
push back TRGCDCWire for this Front-end
Definition: FrontEnd.cc:141
Belle2::TRGCDCFrontEnd::dump_log_outerInside
void dump_log_outerInside(void) const
Dump all the details of _mosb into a .log file, for outerInside FE.
Definition: FrontEnd.cc:1719
Belle2::TRGClock
A class to represent a digitized signal. Unit is nano second.
Definition: Clock.h:43
Belle2::TRGCDCFrontEnd::implementation
static int implementation(const boardType &type, std::ofstream &)
make a VHDL component file.
Definition: FrontEnd.cc:66
Belle2::TRGCDCFrontEnd::getOSB
TRGSignalBundle * getOSB(void) const
output from FrontEnd
Definition: FrontEnd.h:78
Belle2::TRGCDCFrontEnd::~TRGCDCFrontEnd
virtual ~TRGCDCFrontEnd()
Destructor.
Definition: FrontEnd.cc:49