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Belle II Software
release-05-02-19
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15 #define TRG_SHORT_NAMES
16 #define TRGCDC_SHORT_NAMES
19 #include "trg/cdc/JSignalData.h"
20 #include "trg/cdc/JSignal.h"
23 #include "JSignalData.h"
36 TRGCDCJSignalData::TRGCDCJSignalData()
37 : m_vhdlOutputFile(
"vhdlOutput"),
113 if (outFile.is_open()) {
114 outFile <<
"library IEEE;" << endl;
115 outFile <<
"use ieee.std_logic_1164.all;" << endl;
116 outFile <<
"use ieee.numeric_std.all;" << endl;
118 outFile <<
"entity Firmware is" << endl;
119 outFile <<
" PORT ( CLKIN : in STD_LOGIC;" << endl;
120 outFile <<
" INPUT : in std_logic_vector(0 downto 0);" << endl;
121 outFile <<
" OUTPUT : in std_logic_vector(0 downto 0)" << endl;
122 outFile <<
");" << endl;
126 outFile <<
"end Firmware;" << endl;
128 outFile <<
"architecture Behavioral of Firmware is" << endl;
132 outFile <<
"begin" << endl;
134 outFile <<
"-- Main algorithm" << endl;
135 outFile <<
"logic: process (CLKIN) is" << endl;
136 outFile <<
"begin" << endl;
137 outFile <<
" if CLKIN'event and CLKIN='1' then" << endl;
141 outFile <<
" end if;" << endl;
142 outFile <<
"end process;" << endl;
146 outFile <<
"end Behavioral;" << endl;
155 for (map<
string, vector<int> >::const_iterator it =
m_buffers.begin(); it !=
m_buffers.end(); ++it) {
156 string const& name = it->first;
157 int const& type = it->second[0];
158 int const& bitwidth = it->second[1];
159 int const& buffer = it->second[2];
160 string arrayName = (type == 1 ?
"U" :
"S") + to_string(bitwidth) +
"D" + to_string(buffer + 1) +
"Array";
162 m_vhdlDefine +=
"type " + arrayName +
" is array(" + to_string(buffer) +
" downto 0) of " + (type == 1 ?
"unsigned" :
"signed") +
163 "(" + to_string(bitwidth - 1) +
" downto 0);\n";
166 m_vhdlDefine +=
"signal " + name +
"_b : " + arrayName +
" := (others=>(others=>'0'));\n";
169 for (map<
string, vector<int> >::const_iterator it =
m_buffers.begin(); it !=
m_buffers.end(); ++it) {
170 string const& name = it->first;
171 int const& buffer = it->second[2];
172 m_vhdlInProcess += name +
"_b(" + to_string(0) +
") <= " + name +
";\n";
173 for (
int iBuffer = 0; iBuffer < buffer; iBuffer++) {
174 m_vhdlInProcess += name +
"_b(" + to_string(iBuffer + 1) +
") <= " + name +
"_b(" + to_string(iBuffer) +
");\n";
182 for (map<
string, vector<int> >::const_iterator it =
m_signals.begin(); it !=
m_signals.end(); ++it) {
183 string const& name = it->first;
184 int const& type = it->second[0];
185 int const& bitwidth = it->second[1];
187 if (type == 1) typeName =
"unsigned";
188 else if (type == -1) typeName =
"signed";
189 else if (type == 2) typeName =
"std_logic_vector";
191 cout <<
"[Error] TRGCDCJSignalData::signalsVhdlCode() => signal type is unknown." << endl;
193 m_vhdlDefine +=
"signal " + name +
" : " + typeName +
"(" + to_string(bitwidth - 1) +
" downto 0) := (others=>'0');\n";
199 m_vhdlEntry +=
"function decimal_string_to_unsigned(decimal_string: string; wanted_bitwidth: integer) return unsigned is\n";
200 m_vhdlEntry +=
" variable tmp_unsigned: unsigned(wanted_bitwidth-1 downto 0) := (others => '0');\n";
201 m_vhdlEntry +=
" variable character_value: integer;\n";
203 m_vhdlEntry +=
" for string_pos in decimal_string'range loop\n";
204 m_vhdlEntry +=
" case decimal_string(string_pos) is\n";
205 m_vhdlEntry +=
" when '0' => character_value := 0;\n";
206 m_vhdlEntry +=
" when '1' => character_value := 1;\n";
207 m_vhdlEntry +=
" when '2' => character_value := 2;\n";
208 m_vhdlEntry +=
" when '3' => character_value := 3;\n";
209 m_vhdlEntry +=
" when '4' => character_value := 4;\n";
210 m_vhdlEntry +=
" when '5' => character_value := 5;\n";
211 m_vhdlEntry +=
" when '6' => character_value := 6;\n";
212 m_vhdlEntry +=
" when '7' => character_value := 7;\n";
213 m_vhdlEntry +=
" when '8' => character_value := 8;\n";
214 m_vhdlEntry +=
" when '9' => character_value := 9;\n";
215 m_vhdlEntry +=
" when others => report(\"Illegal number\") severity failure;\n";
217 m_vhdlEntry +=
" tmp_unsigned := resize(tmp_unsigned * 10, wanted_bitwidth);\n";
218 m_vhdlEntry +=
" tmp_unsigned := tmp_unsigned + character_value;\n";
221 m_vhdlEntry +=
"end decimal_string_to_unsigned;\n";
222 m_vhdlEntry +=
"function decimal_string_to_signed(decimal_string: string; wanted_bitwidth: positive) return signed is\n";
223 m_vhdlEntry +=
" variable tmp_signed: signed(wanted_bitwidth-1 downto 0) := (others => '0');\n";
224 m_vhdlEntry +=
" variable character_value: integer := 0;\n";
225 m_vhdlEntry +=
" variable sign_value: integer := 1;\n";
227 m_vhdlEntry +=
" for string_pos in decimal_string'range loop\n";
228 m_vhdlEntry +=
" case decimal_string(string_pos) is\n";
230 m_vhdlEntry +=
" when '0' => character_value := 0;\n";
231 m_vhdlEntry +=
" when '1' => character_value := 1;\n";
232 m_vhdlEntry +=
" when '2' => character_value := 2;\n";
233 m_vhdlEntry +=
" when '3' => character_value := 3;\n";
234 m_vhdlEntry +=
" when '4' => character_value := 4;\n";
235 m_vhdlEntry +=
" when '5' => character_value := 5;\n";
236 m_vhdlEntry +=
" when '6' => character_value := 6;\n";
237 m_vhdlEntry +=
" when '7' => character_value := 7;\n";
238 m_vhdlEntry +=
" when '8' => character_value := 8;\n";
239 m_vhdlEntry +=
" when '9' => character_value := 9;\n";
240 m_vhdlEntry +=
" when others => report(\"Illegal number\") severity failure;\n";
242 m_vhdlEntry +=
" tmp_signed := resize(tmp_signed * 10, wanted_bitwidth);\n";
243 m_vhdlEntry +=
" tmp_signed := tmp_signed + sign_value * character_value;\n";
void buffersVhdlCode()
Function to print buffer VHDL code.
std::string m_vhdlOutProcess
Holds VHDL out of process code.
std::map< std::string, std::vector< int > > const & getSignals() const
Gets the signals that were saved for one line of VHDL.
std::string getVhdlInProcess() const
Gets the VHDL code that are in a process statement.
std::map< std::string, std::vector< int > > m_buffers
vector<int> is {type, bitwidth, buffer} Holds all the requried VHDL buffers.
std::string m_vhdlDefine
Holds VHDL define code.
void setVhdlOutputFile(std::string)
Sets the filename for VHDL output.
std::string getVhdlOutProcess() const
Gets the VHDL code that are outside a process statement.
void printToFile()
Utilities Function to print VHDL code.
bool getPrintedToFile() const
Gets the status of m_printedToFile.
void setPrintVhdl(bool)
Sets if to print VHDL output.
std::string m_vhdlOutputFile
Memebers.
bool m_printVhdl
Status if code should be printed.
void setPrintedToFile(bool)
Set to remember that file was printed.
void setVhdlInProcess(std::string)
Set the VHDL code that are in a process statement.
void entryVhdlCode()
Function to print entry VHDL code.
Abstract base class for different kinds of events.
bool m_printedToFile
Statis if VHDL is printed to file.
bool getPrintVhdl() const
Gets the status of m_printVhdl.
std::map< std::string, std::vector< int > > m_signals
Holds all the requried VHDL signals.
std::string m_vhdlEntry
Holds VHDL entry code.
void setVhdlOutProcess(std::string)
Set the VHDL code that is outside a process statement.
std::string getVhdlOutputFile() const
Get the VHDL output code.
std::string m_vhdlInProcess
Holds VHDL process code.
void signalsVhdlCode()
Function to print definition of signal VHDL code.
std::map< std::string, bool > m_arrayType
Holds all the required VHDL types.
std::string getVhdlDefine() const
Gets the VHDL code for define statement.