Belle II Software  release-05-02-19
JSignalData.cc
1 // Intentionally void
2 //-----------------------------------------------------------------------------
3 // $Id$
4 //-----------------------------------------------------------------------------
5 // Filename : JSignalData.cc
6 // Section : TRG CDC
7 // Owner : Jaebak KIM (K.U.)
8 // Email : jbkim@hep.korea.ac.kr
9 //-----------------------------------------------------------------------------
10 // Description : A class for SignalData in CDC Trigger for 3D tracker.
11 //-----------------------------------------------------------------------------
12 // $Log$
13 //-----------------------------------------------------------------------------
14 
15 #define TRG_SHORT_NAMES
16 #define TRGCDC_SHORT_NAMES
17 
18 #ifndef __EXTERNAL__
19 #include "trg/cdc/JSignalData.h"
20 #include "trg/cdc/JSignal.h"
21 #else
22 #include "JSignal.h"
23 #include "JSignalData.h"
24 #endif
25 #include <iostream>
26 #include <fstream>
27 
28 using namespace std;
29 
30 namespace Belle2 {
36  TRGCDCJSignalData::TRGCDCJSignalData()
37  : m_vhdlOutputFile("vhdlOutput"),
38  m_vhdlEntry(""),
39  m_vhdlDefine(""),
40  m_vhdlInProcess(""),
41  m_vhdlOutProcess("")
42  {
43  m_printVhdl = 0;
44  m_printedToFile = 0;
45  }
46 
47  void TRGCDCJSignalData::setVhdlOutputFile(string vhdlOutputFile)
48  {
49  m_vhdlOutputFile = vhdlOutputFile;
50  }
51 
52  void TRGCDCJSignalData::setPrintVhdl(bool printVhdl)
53  {
54  m_printVhdl = printVhdl;
55  }
56 
57  void TRGCDCJSignalData::setPrintedToFile(bool printedToFile)
58  {
59  m_printedToFile = printedToFile;
60  }
61 
62  void TRGCDCJSignalData::setVhdlInProcess(std::string vhdlInProcess)
63  {
64  m_vhdlInProcess = vhdlInProcess;
65  }
66 
67  void TRGCDCJSignalData::setVhdlOutProcess(std::string vhdlOutProcess)
68  {
69  m_vhdlOutProcess = vhdlOutProcess;
70  }
71 
73  {
74  return m_vhdlOutputFile;
75  }
76 
78  {
79  return m_printVhdl;
80  }
81 
83  {
84  return m_printedToFile;
85  }
86 
88  {
89  return m_vhdlInProcess;
90  }
91 
93  {
94  return m_vhdlOutProcess;
95  }
96 
98  {
99  return m_vhdlDefine;
100  }
101 
102  std::map<std::string, std::vector<int> > const& TRGCDCJSignalData::getSignals() const
103  {
104  return m_signals;
105  }
106 
107 
109  {
110  // Write to file.
111  ofstream outFile;
112  outFile.open(m_vhdlOutputFile);
113  if (outFile.is_open()) {
114  outFile << "library IEEE;" << endl;
115  outFile << "use ieee.std_logic_1164.all;" << endl;
116  outFile << "use ieee.numeric_std.all;" << endl;
117  outFile << endl;
118  outFile << "entity Firmware is" << endl;
119  outFile << " PORT ( CLKIN : in STD_LOGIC;" << endl;
120  outFile << " INPUT : in std_logic_vector(0 downto 0);" << endl;
121  outFile << " OUTPUT : in std_logic_vector(0 downto 0)" << endl;
122  outFile << ");" << endl;
123  outFile << endl;
124  outFile << m_vhdlEntry << endl;
125  outFile << endl;
126  outFile << "end Firmware;" << endl;
127  outFile << endl;
128  outFile << "architecture Behavioral of Firmware is" << endl;
129  outFile << endl;
130  outFile << m_vhdlDefine << endl;
131  outFile << endl;
132  outFile << "begin" << endl;
133  outFile << endl;
134  outFile << "-- Main algorithm" << endl;
135  outFile << "logic: process (CLKIN) is" << endl;
136  outFile << "begin" << endl;
137  outFile << " if CLKIN'event and CLKIN='1' then" << endl;
138  outFile << endl;
139  outFile << m_vhdlInProcess << endl;
140  outFile << endl;
141  outFile << " end if;" << endl;
142  outFile << "end process;" << endl;
143  outFile << endl;
144  outFile << m_vhdlOutProcess << endl;
145  outFile << endl;
146  outFile << "end Behavioral;" << endl;
147  outFile.close();
148  m_printedToFile = 1;
149  }
150  }
151 
153  {
154  // Define.
155  for (map<string, vector<int> >::const_iterator it = m_buffers.begin(); it != m_buffers.end(); ++it) {
156  string const& name = it->first;
157  int const& type = it->second[0];
158  int const& bitwidth = it->second[1];
159  int const& buffer = it->second[2];
160  string arrayName = (type == 1 ? "U" : "S") + to_string(bitwidth) + "D" + to_string(buffer + 1) + "Array";
161  if (m_arrayType.find(arrayName) == m_arrayType.end()) {
162  m_vhdlDefine += "type " + arrayName + " is array(" + to_string(buffer) + " downto 0) of " + (type == 1 ? "unsigned" : "signed") +
163  "(" + to_string(bitwidth - 1) + " downto 0);\n";
164  m_arrayType[arrayName] = 1;
165  }
166  m_vhdlDefine += "signal " + name + "_b : " + arrayName + " := (others=>(others=>'0'));\n";
167  }
168  // Process.
169  for (map<string, vector<int> >::const_iterator it = m_buffers.begin(); it != m_buffers.end(); ++it) {
170  string const& name = it->first;
171  int const& buffer = it->second[2];
172  m_vhdlInProcess += name + "_b(" + to_string(0) + ") <= " + name + ";\n";
173  for (int iBuffer = 0; iBuffer < buffer; iBuffer++) {
174  m_vhdlInProcess += name + "_b(" + to_string(iBuffer + 1) + ") <= " + name + "_b(" + to_string(iBuffer) + ");\n";
175  }
176  }
177 
178  }
179 
181  {
182  for (map<string, vector<int> >::const_iterator it = m_signals.begin(); it != m_signals.end(); ++it) {
183  string const& name = it->first;
184  int const& type = it->second[0];
185  int const& bitwidth = it->second[1];
186  string typeName;
187  if (type == 1) typeName = "unsigned";
188  else if (type == -1) typeName = "signed";
189  else if (type == 2) typeName = "std_logic_vector";
190  else {
191  cout << "[Error] TRGCDCJSignalData::signalsVhdlCode() => signal type is unknown." << endl;
192  }
193  m_vhdlDefine += "signal " + name + " : " + typeName + "(" + to_string(bitwidth - 1) + " downto 0) := (others=>'0');\n";
194  }
195  }
196 
198  {
199  m_vhdlEntry += "function decimal_string_to_unsigned(decimal_string: string; wanted_bitwidth: integer) return unsigned is\n";
200  m_vhdlEntry += " variable tmp_unsigned: unsigned(wanted_bitwidth-1 downto 0) := (others => '0');\n";
201  m_vhdlEntry += " variable character_value: integer;\n";
202  m_vhdlEntry += "begin\n";
203  m_vhdlEntry += " for string_pos in decimal_string'range loop\n";
204  m_vhdlEntry += " case decimal_string(string_pos) is\n";
205  m_vhdlEntry += " when '0' => character_value := 0;\n";
206  m_vhdlEntry += " when '1' => character_value := 1;\n";
207  m_vhdlEntry += " when '2' => character_value := 2;\n";
208  m_vhdlEntry += " when '3' => character_value := 3;\n";
209  m_vhdlEntry += " when '4' => character_value := 4;\n";
210  m_vhdlEntry += " when '5' => character_value := 5;\n";
211  m_vhdlEntry += " when '6' => character_value := 6;\n";
212  m_vhdlEntry += " when '7' => character_value := 7;\n";
213  m_vhdlEntry += " when '8' => character_value := 8;\n";
214  m_vhdlEntry += " when '9' => character_value := 9;\n";
215  m_vhdlEntry += " when others => report(\"Illegal number\") severity failure;\n";
216  m_vhdlEntry += " end case;\n";
217  m_vhdlEntry += " tmp_unsigned := resize(tmp_unsigned * 10, wanted_bitwidth);\n";
218  m_vhdlEntry += " tmp_unsigned := tmp_unsigned + character_value;\n";
219  m_vhdlEntry += " end loop;\n";
220  m_vhdlEntry += " return tmp_unsigned;\n";
221  m_vhdlEntry += "end decimal_string_to_unsigned;\n";
222  m_vhdlEntry += "function decimal_string_to_signed(decimal_string: string; wanted_bitwidth: positive) return signed is\n";
223  m_vhdlEntry += " variable tmp_signed: signed(wanted_bitwidth-1 downto 0) := (others => '0');\n";
224  m_vhdlEntry += " variable character_value: integer := 0;\n";
225  m_vhdlEntry += " variable sign_value: integer := 1;\n";
226  m_vhdlEntry += "begin\n";
227  m_vhdlEntry += " for string_pos in decimal_string'range loop\n";
228  m_vhdlEntry += " case decimal_string(string_pos) is\n";
229  m_vhdlEntry += " when '-' => sign_value := -1;\n";
230  m_vhdlEntry += " when '0' => character_value := 0;\n";
231  m_vhdlEntry += " when '1' => character_value := 1;\n";
232  m_vhdlEntry += " when '2' => character_value := 2;\n";
233  m_vhdlEntry += " when '3' => character_value := 3;\n";
234  m_vhdlEntry += " when '4' => character_value := 4;\n";
235  m_vhdlEntry += " when '5' => character_value := 5;\n";
236  m_vhdlEntry += " when '6' => character_value := 6;\n";
237  m_vhdlEntry += " when '7' => character_value := 7;\n";
238  m_vhdlEntry += " when '8' => character_value := 8;\n";
239  m_vhdlEntry += " when '9' => character_value := 9;\n";
240  m_vhdlEntry += " when others => report(\"Illegal number\") severity failure;\n";
241  m_vhdlEntry += " end case;\n";
242  m_vhdlEntry += " tmp_signed := resize(tmp_signed * 10, wanted_bitwidth);\n";
243  m_vhdlEntry += " tmp_signed := tmp_signed + sign_value * character_value;\n";
244  m_vhdlEntry += " end loop;\n";
245  m_vhdlEntry += " return tmp_signed;\n";
246  m_vhdlEntry += "end decimal_string_to_signed;\n";
247  }
248 
250 }
Belle2::TRGCDCJSignalData::buffersVhdlCode
void buffersVhdlCode()
Function to print buffer VHDL code.
Definition: JSignalData.cc:152
Belle2::TRGCDCJSignalData::m_vhdlOutProcess
std::string m_vhdlOutProcess
Holds VHDL out of process code.
Definition: JSignalData.h:88
Belle2::TRGCDCJSignalData::getSignals
std::map< std::string, std::vector< int > > const & getSignals() const
Gets the signals that were saved for one line of VHDL.
Definition: JSignalData.cc:102
Belle2::TRGCDCJSignalData::getVhdlInProcess
std::string getVhdlInProcess() const
Gets the VHDL code that are in a process statement.
Definition: JSignalData.cc:87
Belle2::TRGCDCJSignalData::m_buffers
std::map< std::string, std::vector< int > > m_buffers
vector<int> is {type, bitwidth, buffer} Holds all the requried VHDL buffers.
Definition: JSignalData.h:95
Belle2::TRGCDCJSignalData::m_vhdlDefine
std::string m_vhdlDefine
Holds VHDL define code.
Definition: JSignalData.h:84
Belle2::TRGCDCJSignalData::setVhdlOutputFile
void setVhdlOutputFile(std::string)
Sets the filename for VHDL output.
Definition: JSignalData.cc:47
Belle2::TRGCDCJSignalData::getVhdlOutProcess
std::string getVhdlOutProcess() const
Gets the VHDL code that are outside a process statement.
Definition: JSignalData.cc:92
Belle2::TRGCDCJSignalData::printToFile
void printToFile()
Utilities Function to print VHDL code.
Definition: JSignalData.cc:108
Belle2::TRGCDCJSignalData::getPrintedToFile
bool getPrintedToFile() const
Gets the status of m_printedToFile.
Definition: JSignalData.cc:82
Belle2::TRGCDCJSignalData::setPrintVhdl
void setPrintVhdl(bool)
Sets if to print VHDL output.
Definition: JSignalData.cc:52
Belle2::TRGCDCJSignalData::m_vhdlOutputFile
std::string m_vhdlOutputFile
Memebers.
Definition: JSignalData.h:80
Belle2::TRGCDCJSignalData::m_printVhdl
bool m_printVhdl
Status if code should be printed.
Definition: JSignalData.h:90
Belle2::TRGCDCJSignalData::setPrintedToFile
void setPrintedToFile(bool)
Set to remember that file was printed.
Definition: JSignalData.cc:57
Belle2::TRGCDCJSignalData::setVhdlInProcess
void setVhdlInProcess(std::string)
Set the VHDL code that are in a process statement.
Definition: JSignalData.cc:62
Belle2::TRGCDCJSignalData::entryVhdlCode
void entryVhdlCode()
Function to print entry VHDL code.
Definition: JSignalData.cc:197
Belle2
Abstract base class for different kinds of events.
Definition: MillepedeAlgorithm.h:19
Belle2::TRGCDCJSignalData::m_printedToFile
bool m_printedToFile
Statis if VHDL is printed to file.
Definition: JSignalData.h:92
Belle2::TRGCDCJSignalData::getPrintVhdl
bool getPrintVhdl() const
Gets the status of m_printVhdl.
Definition: JSignalData.cc:77
Belle2::TRGCDCJSignalData::m_signals
std::map< std::string, std::vector< int > > m_signals
Holds all the requried VHDL signals.
Definition: JSignalData.h:97
Belle2::TRGCDCJSignalData::m_vhdlEntry
std::string m_vhdlEntry
Holds VHDL entry code.
Definition: JSignalData.h:82
Belle2::TRGCDCJSignalData::setVhdlOutProcess
void setVhdlOutProcess(std::string)
Set the VHDL code that is outside a process statement.
Definition: JSignalData.cc:67
Belle2::TRGCDCJSignalData::getVhdlOutputFile
std::string getVhdlOutputFile() const
Get the VHDL output code.
Definition: JSignalData.cc:72
Belle2::TRGCDCJSignalData::m_vhdlInProcess
std::string m_vhdlInProcess
Holds VHDL process code.
Definition: JSignalData.h:86
Belle2::TRGCDCJSignalData::signalsVhdlCode
void signalsVhdlCode()
Function to print definition of signal VHDL code.
Definition: JSignalData.cc:180
Belle2::TRGCDCJSignalData::m_arrayType
std::map< std::string, bool > m_arrayType
Holds all the required VHDL types.
Definition: JSignalData.h:99
Belle2::TRGCDCJSignalData::getVhdlDefine
std::string getVhdlDefine() const
Gets the VHDL code for define statement.
Definition: JSignalData.cc:97