CDCTriggerTSFFirmwareModule.h

/**************************************************************************
 * basf2 (Belle II Analysis Software Framework)                           *
 * Author: The Belle II Collaboration                                     *
 *                                                                        *
 * See git log for contributors and copyright holders.                    *
 * This file is licensed under LGPL-3.0, see LICENSE.md.                  *
 **************************************************************************/
#pragma once
#include <framework/core/Module.h>
#include <cdc/dataobjects/CDCHit.h>
#include <framework/datastore/StoreArray.h>
#include <trg/cdc/dataobjects/Bitstream.h>
#include <trg/cdc/dataobjects/CDCTriggerSegmentHit.h>
#include <trg/cdc/Cosim.h>
 
#include <string>
#include <vector>
#include <bitset>
#include <array>
#include <tuple>
#include <unordered_map>
 
#include <unistd.h>
#include <cstdio>
 
namespace Belle2 {
  namespace CDCTrigger {
    enum class Priority : unsigned char {nothing, first, second};
    std::unordered_map<unsigned, Priority> toPriorityMap = {{0, Priority::nothing},
      {1, Priority::second},
      {2, Priority::second},
      {3, Priority::first}
    };
    Priority toPriority(unsigned priorityPosition)
    {
      return toPriorityMap[priorityPosition];
    }
    enum MergerOut : long unsigned int {priorityTime, fastestTime, edgeTime, hitmap, secondPriorityHit};
  }
 
  class CDCTriggerTSFFirmwareModule : public Module {
  public:
    CDCTriggerTSFFirmwareModule();
 
    virtual ~CDCTriggerTSFFirmwareModule();
 
    void initialize() override;
 
    void terminate() override;
 
    void event() override;
 
    static constexpr int m_nSubModules = 5;
 
    static constexpr std::array<int, 9> nMergers = {10, 10, 12, 14, 16, 18, 20, 22, 24};
 
    static constexpr std::array<int, m_nSubModules> nAxialMergers = {10, 12, 16, 20, 24};
 
    static constexpr int nTrackers = 4;
 
    static constexpr int mergerWidth = 256;
 
    static constexpr int width_out = 429;
 
    static constexpr int nWiresInMerger = 80;
 
    static constexpr int nCellsInLayer = 16;
 
    static constexpr int nSegmentsInMerger = 16;
 
    static constexpr size_t timeWidth = 4;
 
    static constexpr int m_nClockPerEvent = 44;
 
    static constexpr int clockPeriod = 16;
 
  protected:
    std::string m_hitCollectionName;
 
    std::string m_outputCollectionName;
 
    std::string m_outputBitstreamNameTo2D;
 
    std::string m_outputBitstreamNameToETF;
 
    Belle2::StoreArray<CDCHit> m_cdcHits;
 
    using outputVector = std::array<char, width_out>;
    using outputArray = std::array<outputVector, nTrackers>;
 
    using signalBus = std::array<outputArray, m_nSubModules>;
    using signalBitStream = Bitstream<signalBus>;
 
    StoreArray<signalBitStream> m_bitsTo2D;
 
    StoreArray<CDCTriggerSegmentHit> m_tsHits;
 
    bool m_mergerOnly;
 
    bool m_simulateCC;
 
    std::vector<bool> m_stubLUT;
 
    int m_debugLevel = 0; //TODO what should be default?
 
    int m_TDCCountForT0 = 4988;
 
    bool m_allPositiveTime = true;
 
    std::string lib_extension = ".so";
    std::string cwd = getcurrentdir();
    std::string design_libname_pre = cwd + "/xsim.dir/tsf";
    std::string design_libname_post = "/xsimk" + lib_extension;
    std::string simengine_libname = "librdi_simulator_kernel" + lib_extension;
    std::string wdbName_pre = "tsf";
    std::string wdbName_post = ".wdb";
 
    /* static constexpr char one_val  = 3; */
    /* static constexpr char zero_val = 2; */
 
    std::array<pid_t, m_nSubModules> m_pid;
 
    using mergerVector = std::bitset<mergerWidth>;
    using mergerOutput = std::vector<mergerVector>;
    using mergerOutArray = std::array<mergerOutput, m_nSubModules>;
    mergerOutArray outputFromMerger;
 
    using inputVector = std::array<char, mergerWidth>;
    using inputFromMerger = std::vector<inputVector>;
    using inputToTSFArray = std::array<inputFromMerger, m_nSubModules>;
    inputToTSFArray inputToTSF;
 
    std::array<outputArray, m_nSubModules> outputToTracker;
 
    template<int iSL>
    char* getData(inputToTSFArray);
 
    using streamPair = std::array<FILE*, 2>;
    std::array<streamPair, m_nSubModules> stream;
 
    std::array<std::array<int, 2>, m_nSubModules> inputFileDescriptor;
    std::array<std::array<int, 2>, m_nSubModules> outputFileDescriptor;
 
    void write(const char* message, FILE* outstream);
 
    outputArray read(FILE* instream);
 
    std::istream* ins = nullptr;
 
    /**************************************************
     *  Merger simulation
     **************************************************/
 
    using timeVec = std::bitset<timeWidth>;
    template<size_t nEdges>
    using mergerStructElement = std::tuple <
                                std::array<timeVec, nSegmentsInMerger>,
                                std::array<timeVec, nSegmentsInMerger>,
                                std::array<timeVec, nEdges>,
                                std::array<std::bitset<nWiresInMerger>, 1>,
                                std::array<std::bitset<nSegmentsInMerger>, 1> >;
    template<size_t nEdges>
    using mergerStruct = std::vector<mergerStructElement<nEdges> >;
    std::map<unsigned, mergerStruct<5> > dataAcrossClocks;
 
    using registeredStructElement = std::array<std::bitset<nCellsInLayer>, 3>;
    using registeredStruct = std::vector<registeredStructElement>;
 
    using priorityHitInMerger = std::map<unsigned, int>;
    using priorityHitStructInSL = std::vector<priorityHitInMerger>;
    using priorityHitStructInClock = std::map<unsigned, priorityHitStructInSL>;
    using priorityHitStruct = std::array<priorityHitStructInClock, m_nClockPerEvent>;
    priorityHitStruct m_priorityHit;
    std::vector<std::vector<int> > iAxialHitInClock;
 
    using WireSet = std::vector<short>;
    using TSMap = std::unordered_map<short, WireSet>;
    std::array<TSMap, 2> m_tsMap;
 
    using edgeMap = std::unordered_map<unsigned short, timeVec*>;
    using cellList = std::vector<unsigned short>;
    std::array<cellList, 5> innerInvEdge = {cellList {31},
                                            cellList {64},
                                            cellList {32, 48, 64, 65},
                                            cellList {31, 47, 62, 63, 78},
                                            cellList {63, 79}
                                           };
 
    std::array<cellList, 3> outerInvEdge = {cellList {63},
                                            cellList {0, 64},
                                            cellList {15, 31, 63, 79}
                                           };
    using edgeList = std::unordered_map<unsigned short, std::vector<unsigned short>>;
    std::array<edgeList, 2> m_edge;
 
    int m_iFirstHit = std::numeric_limits<int>::quiet_NaN();
 
    CDCTrigger::Priority priority(int index);
 
    unsigned short trgTime(int index, int iFirstHit);
 
    unsigned short mergerCellID(int index);
 
    unsigned short mergerNumber(int index);
 
    WireSet segmentID(int iHit);
 
    std::bitset<4> timeStamp(int index, int iFirstHit);
 
    void computeEdges();
 
    void initializeMerger();
 
    void simulateMerger(unsigned iclock);
 
    template<CDCTrigger::MergerOut field, size_t width>
    void pack(inputVector::reverse_iterator& rInput,
              unsigned number, mergerStructElement<5>& output);
 
    bool notHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement& reg);
 
    void registerHit(CDCTrigger::MergerOut field, unsigned iTS, registeredStructElement& reg);
 
    void saveFirmwareOutput();
 
    void saveFastOutput(short iclock);
 
    void setSecondPriority(unsigned priTS,
                           unsigned iHit,
                           timeVec hitTime,
                           unsigned lr,
                           mergerStructElement<5>& mergerData,
                           registeredStructElement& registeredCell,
                           priorityHitInMerger& priorityHit);
  };
}