13#define TRG_SHORT_NAMES
14#define TRGCDC_SHORT_NAMES
17#include "trg/cdc/JSignalData.h"
18#include "trg/cdc/JSignal.h"
21#include "JSignalData.h"
35 : m_vhdlOutputFile(
"vhdlOutput"),
111 if (outFile.is_open()) {
112 outFile <<
"library IEEE;" << endl;
113 outFile <<
"use ieee.std_logic_1164.all;" << endl;
114 outFile <<
"use ieee.numeric_std.all;" << endl;
116 outFile <<
"entity Firmware is" << endl;
117 outFile <<
" PORT ( CLKIN : in STD_LOGIC;" << endl;
118 outFile <<
" INPUT : in std_logic_vector(0 downto 0);" << endl;
119 outFile <<
" OUTPUT : in std_logic_vector(0 downto 0)" << endl;
120 outFile <<
");" << endl;
124 outFile <<
"end Firmware;" << endl;
126 outFile <<
"architecture Behavioral of Firmware is" << endl;
130 outFile <<
"begin" << endl;
132 outFile <<
"-- Main algorithm" << endl;
133 outFile <<
"logic: process (CLKIN) is" << endl;
134 outFile <<
"begin" << endl;
135 outFile <<
" if CLKIN'event and CLKIN='1' then" << endl;
139 outFile <<
" end if;" << endl;
140 outFile <<
"end process;" << endl;
144 outFile <<
"end Behavioral;" << endl;
153 for (map<
string, vector<int> >::const_iterator it =
m_buffers.begin(); it !=
m_buffers.end(); ++it) {
154 string const& name = it->first;
155 int const& type = it->second[0];
156 int const& bitwidth = it->second[1];
157 int const& buffer = it->second[2];
158 string arrayName = (type == 1 ?
"U" :
"S") + to_string(bitwidth) +
"D" + to_string(buffer + 1) +
"Array";
160 m_vhdlDefine +=
"type " + arrayName +
" is array(" + to_string(buffer) +
" downto 0) of " + (type == 1 ?
"unsigned" :
"signed") +
161 "(" + to_string(bitwidth - 1) +
" downto 0);\n";
164 m_vhdlDefine +=
"signal " + name +
"_b : " + arrayName +
" := (others=>(others=>'0'));\n";
167 for (map<
string, vector<int> >::const_iterator it =
m_buffers.begin(); it !=
m_buffers.end(); ++it) {
168 string const& name = it->first;
169 int const& buffer = it->second[2];
170 m_vhdlInProcess += name +
"_b(" + to_string(0) +
") <= " + name +
";\n";
171 for (
int iBuffer = 0; iBuffer < buffer; iBuffer++) {
172 m_vhdlInProcess += name +
"_b(" + to_string(iBuffer + 1) +
") <= " + name +
"_b(" + to_string(iBuffer) +
");\n";
180 for (map<
string, vector<int> >::const_iterator it =
m_signals.begin(); it !=
m_signals.end(); ++it) {
181 string const& name = it->first;
182 int const& type = it->second[0];
183 int const& bitwidth = it->second[1];
185 if (type == 1) typeName =
"unsigned";
186 else if (type == -1) typeName =
"signed";
187 else if (type == 2) typeName =
"std_logic_vector";
189 cout <<
"[Error] TRGCDCJSignalData::signalsVhdlCode() => signal type is unknown." << endl;
191 m_vhdlDefine +=
"signal " + name +
" : " + typeName +
"(" + to_string(bitwidth - 1) +
" downto 0) := (others=>'0');\n";
197 m_vhdlEntry +=
"function decimal_string_to_unsigned(decimal_string: string; wanted_bitwidth: integer) return unsigned is\n";
198 m_vhdlEntry +=
" variable tmp_unsigned: unsigned(wanted_bitwidth-1 downto 0) := (others => '0');\n";
199 m_vhdlEntry +=
" variable character_value: integer;\n";
201 m_vhdlEntry +=
" for string_pos in decimal_string'range loop\n";
202 m_vhdlEntry +=
" case decimal_string(string_pos) is\n";
203 m_vhdlEntry +=
" when '0' => character_value := 0;\n";
204 m_vhdlEntry +=
" when '1' => character_value := 1;\n";
205 m_vhdlEntry +=
" when '2' => character_value := 2;\n";
206 m_vhdlEntry +=
" when '3' => character_value := 3;\n";
207 m_vhdlEntry +=
" when '4' => character_value := 4;\n";
208 m_vhdlEntry +=
" when '5' => character_value := 5;\n";
209 m_vhdlEntry +=
" when '6' => character_value := 6;\n";
210 m_vhdlEntry +=
" when '7' => character_value := 7;\n";
211 m_vhdlEntry +=
" when '8' => character_value := 8;\n";
212 m_vhdlEntry +=
" when '9' => character_value := 9;\n";
213 m_vhdlEntry +=
" when others => report(\"Illegal number\") severity failure;\n";
215 m_vhdlEntry +=
" tmp_unsigned := resize(tmp_unsigned * 10, wanted_bitwidth);\n";
216 m_vhdlEntry +=
" tmp_unsigned := tmp_unsigned + character_value;\n";
219 m_vhdlEntry +=
"end decimal_string_to_unsigned;\n";
220 m_vhdlEntry +=
"function decimal_string_to_signed(decimal_string: string; wanted_bitwidth: positive) return signed is\n";
221 m_vhdlEntry +=
" variable tmp_signed: signed(wanted_bitwidth-1 downto 0) := (others => '0');\n";
222 m_vhdlEntry +=
" variable character_value: integer := 0;\n";
223 m_vhdlEntry +=
" variable sign_value: integer := 1;\n";
225 m_vhdlEntry +=
" for string_pos in decimal_string'range loop\n";
226 m_vhdlEntry +=
" case decimal_string(string_pos) is\n";
228 m_vhdlEntry +=
" when '0' => character_value := 0;\n";
229 m_vhdlEntry +=
" when '1' => character_value := 1;\n";
230 m_vhdlEntry +=
" when '2' => character_value := 2;\n";
231 m_vhdlEntry +=
" when '3' => character_value := 3;\n";
232 m_vhdlEntry +=
" when '4' => character_value := 4;\n";
233 m_vhdlEntry +=
" when '5' => character_value := 5;\n";
234 m_vhdlEntry +=
" when '6' => character_value := 6;\n";
235 m_vhdlEntry +=
" when '7' => character_value := 7;\n";
236 m_vhdlEntry +=
" when '8' => character_value := 8;\n";
237 m_vhdlEntry +=
" when '9' => character_value := 9;\n";
238 m_vhdlEntry +=
" when others => report(\"Illegal number\") severity failure;\n";
240 m_vhdlEntry +=
" tmp_signed := resize(tmp_signed * 10, wanted_bitwidth);\n";
241 m_vhdlEntry +=
" tmp_signed := tmp_signed + sign_value * character_value;\n";
bool m_printVhdl
Status if code should be printed.
std::string m_vhdlInProcess
Holds VHDL process code.
std::string m_vhdlOutputFile
Memebers.
std::string m_vhdlEntry
Holds VHDL entry code.
std::map< std::string, bool > m_arrayType
Holds all the required VHDL types.
std::map< std::string, std::vector< int > > m_buffers
vector<int> is {type, bitwidth, buffer} Holds all the requried VHDL buffers.
std::map< std::string, std::vector< int > > m_signals
Holds all the requried VHDL signals.
bool m_printedToFile
Statis if VHDL is printed to file.
std::string m_vhdlDefine
Holds VHDL define code.
std::string m_vhdlOutProcess
Holds VHDL out of process code.
void setPrintedToFile(bool)
Set to remember that file was printed.
std::string getVhdlInProcess() const
Gets the VHDL code that are in a process statement.
void printToFile()
Utilities Function to print VHDL code.
std::string getVhdlOutProcess() const
Gets the VHDL code that are outside a process statement.
bool getPrintVhdl() const
Gets the status of m_printVhdl.
void setVhdlInProcess(const std::string &)
Set the VHDL code that are in a process statement.
void setVhdlOutProcess(const std::string &)
Set the VHDL code that is outside a process statement.
bool getPrintedToFile() const
Gets the status of m_printedToFile.
std::map< std::string, std::vector< int > > const & getSignals() const
Gets the signals that were saved for one line of VHDL.
std::string getVhdlOutputFile() const
Get the VHDL output code.
std::string getVhdlDefine() const
Gets the VHDL code for define statement.
void entryVhdlCode()
Function to print entry VHDL code.
void signalsVhdlCode()
Function to print definition of signal VHDL code.
void setVhdlOutputFile(const std::string &)
Sets the filename for VHDL output.
void buffersVhdlCode()
Function to print buffer VHDL code.
void setPrintVhdl(bool)
Sets if to print VHDL output.
TRGCDCJSignalData()
Constructor for class.
Abstract base class for different kinds of events.