Belle II Software development
JSignalData.cc
1/**************************************************************************
2 * basf2 (Belle II Analysis Software Framework) *
3 * Author: The Belle II Collaboration *
4 * *
5 * See git log for contributors and copyright holders. *
6 * This file is licensed under LGPL-3.0, see LICENSE.md. *
7 **************************************************************************/
8
9//-----------------------------------------------------------------------------
10// Description : A class for SignalData in CDC Trigger for 3D tracker.
11//-----------------------------------------------------------------------------
12
13#define TRG_SHORT_NAMES
14#define TRGCDC_SHORT_NAMES
15
16#ifndef __EXTERNAL__
17#include "trg/cdc/JSignalData.h"
18#include "trg/cdc/JSignal.h"
19#else
20#include "JSignal.h"
21#include "JSignalData.h"
22#endif
23#include <iostream>
24#include <fstream>
25
26using namespace std;
27
28namespace Belle2 {
35 : m_vhdlOutputFile("vhdlOutput"),
36 m_vhdlEntry(""),
37 m_vhdlDefine(""),
38 m_vhdlInProcess(""),
39 m_vhdlOutProcess("")
40 {
41 m_printVhdl = 0;
43 }
44
45 void TRGCDCJSignalData::setVhdlOutputFile(const string& vhdlOutputFile)
46 {
47 m_vhdlOutputFile = vhdlOutputFile;
48 }
49
51 {
52 m_printVhdl = printVhdl;
53 }
54
55 void TRGCDCJSignalData::setPrintedToFile(bool printedToFile)
56 {
57 m_printedToFile = printedToFile;
58 }
59
60 void TRGCDCJSignalData::setVhdlInProcess(const std::string& vhdlInProcess)
61 {
62 m_vhdlInProcess = vhdlInProcess;
63 }
64
65 void TRGCDCJSignalData::setVhdlOutProcess(const std::string& vhdlOutProcess)
66 {
67 m_vhdlOutProcess = vhdlOutProcess;
68 }
69
71 {
72 return m_vhdlOutputFile;
73 }
74
76 {
77 return m_printVhdl;
78 }
79
81 {
82 return m_printedToFile;
83 }
84
86 {
87 return m_vhdlInProcess;
88 }
89
91 {
92 return m_vhdlOutProcess;
93 }
94
96 {
97 return m_vhdlDefine;
98 }
99
100 std::map<std::string, std::vector<int> > const& TRGCDCJSignalData::getSignals() const
101 {
102 return m_signals;
103 }
104
105
107 {
108 // Write to file.
109 ofstream outFile;
110 outFile.open(m_vhdlOutputFile);
111 if (outFile.is_open()) {
112 outFile << "library IEEE;" << endl;
113 outFile << "use ieee.std_logic_1164.all;" << endl;
114 outFile << "use ieee.numeric_std.all;" << endl;
115 outFile << endl;
116 outFile << "entity Firmware is" << endl;
117 outFile << " PORT ( CLKIN : in STD_LOGIC;" << endl;
118 outFile << " INPUT : in std_logic_vector(0 downto 0);" << endl;
119 outFile << " OUTPUT : in std_logic_vector(0 downto 0)" << endl;
120 outFile << ");" << endl;
121 outFile << endl;
122 outFile << m_vhdlEntry << endl;
123 outFile << endl;
124 outFile << "end Firmware;" << endl;
125 outFile << endl;
126 outFile << "architecture Behavioral of Firmware is" << endl;
127 outFile << endl;
128 outFile << m_vhdlDefine << endl;
129 outFile << endl;
130 outFile << "begin" << endl;
131 outFile << endl;
132 outFile << "-- Main algorithm" << endl;
133 outFile << "logic: process (CLKIN) is" << endl;
134 outFile << "begin" << endl;
135 outFile << " if CLKIN'event and CLKIN='1' then" << endl;
136 outFile << endl;
137 outFile << m_vhdlInProcess << endl;
138 outFile << endl;
139 outFile << " end if;" << endl;
140 outFile << "end process;" << endl;
141 outFile << endl;
142 outFile << m_vhdlOutProcess << endl;
143 outFile << endl;
144 outFile << "end Behavioral;" << endl;
145 outFile.close();
146 m_printedToFile = 1;
147 }
148 }
149
151 {
152 // Define.
153 for (map<string, vector<int> >::const_iterator it = m_buffers.begin(); it != m_buffers.end(); ++it) {
154 string const& name = it->first;
155 int const& type = it->second[0];
156 int const& bitwidth = it->second[1];
157 int const& buffer = it->second[2];
158 string arrayName = (type == 1 ? "U" : "S") + to_string(bitwidth) + "D" + to_string(buffer + 1) + "Array";
159 if (m_arrayType.find(arrayName) == m_arrayType.end()) {
160 m_vhdlDefine += "type " + arrayName + " is array(" + to_string(buffer) + " downto 0) of " + (type == 1 ? "unsigned" : "signed") +
161 "(" + to_string(bitwidth - 1) + " downto 0);\n";
162 m_arrayType[arrayName] = 1;
163 }
164 m_vhdlDefine += "signal " + name + "_b : " + arrayName + " := (others=>(others=>'0'));\n";
165 }
166 // Process.
167 for (map<string, vector<int> >::const_iterator it = m_buffers.begin(); it != m_buffers.end(); ++it) {
168 string const& name = it->first;
169 int const& buffer = it->second[2];
170 m_vhdlInProcess += name + "_b(" + to_string(0) + ") <= " + name + ";\n";
171 for (int iBuffer = 0; iBuffer < buffer; iBuffer++) {
172 m_vhdlInProcess += name + "_b(" + to_string(iBuffer + 1) + ") <= " + name + "_b(" + to_string(iBuffer) + ");\n";
173 }
174 }
175
176 }
177
179 {
180 for (map<string, vector<int> >::const_iterator it = m_signals.begin(); it != m_signals.end(); ++it) {
181 string const& name = it->first;
182 int const& type = it->second[0];
183 int const& bitwidth = it->second[1];
184 string typeName;
185 if (type == 1) typeName = "unsigned";
186 else if (type == -1) typeName = "signed";
187 else if (type == 2) typeName = "std_logic_vector";
188 else {
189 cout << "[Error] TRGCDCJSignalData::signalsVhdlCode() => signal type is unknown." << endl;
190 }
191 m_vhdlDefine += "signal " + name + " : " + typeName + "(" + to_string(bitwidth - 1) + " downto 0) := (others=>'0');\n";
192 }
193 }
194
196 {
197 m_vhdlEntry += "function decimal_string_to_unsigned(decimal_string: string; wanted_bitwidth: integer) return unsigned is\n";
198 m_vhdlEntry += " variable tmp_unsigned: unsigned(wanted_bitwidth-1 downto 0) := (others => '0');\n";
199 m_vhdlEntry += " variable character_value: integer;\n";
200 m_vhdlEntry += "begin\n";
201 m_vhdlEntry += " for string_pos in decimal_string'range loop\n";
202 m_vhdlEntry += " case decimal_string(string_pos) is\n";
203 m_vhdlEntry += " when '0' => character_value := 0;\n";
204 m_vhdlEntry += " when '1' => character_value := 1;\n";
205 m_vhdlEntry += " when '2' => character_value := 2;\n";
206 m_vhdlEntry += " when '3' => character_value := 3;\n";
207 m_vhdlEntry += " when '4' => character_value := 4;\n";
208 m_vhdlEntry += " when '5' => character_value := 5;\n";
209 m_vhdlEntry += " when '6' => character_value := 6;\n";
210 m_vhdlEntry += " when '7' => character_value := 7;\n";
211 m_vhdlEntry += " when '8' => character_value := 8;\n";
212 m_vhdlEntry += " when '9' => character_value := 9;\n";
213 m_vhdlEntry += " when others => report(\"Illegal number\") severity failure;\n";
214 m_vhdlEntry += " end case;\n";
215 m_vhdlEntry += " tmp_unsigned := resize(tmp_unsigned * 10, wanted_bitwidth);\n";
216 m_vhdlEntry += " tmp_unsigned := tmp_unsigned + character_value;\n";
217 m_vhdlEntry += " end loop;\n";
218 m_vhdlEntry += " return tmp_unsigned;\n";
219 m_vhdlEntry += "end decimal_string_to_unsigned;\n";
220 m_vhdlEntry += "function decimal_string_to_signed(decimal_string: string; wanted_bitwidth: positive) return signed is\n";
221 m_vhdlEntry += " variable tmp_signed: signed(wanted_bitwidth-1 downto 0) := (others => '0');\n";
222 m_vhdlEntry += " variable character_value: integer := 0;\n";
223 m_vhdlEntry += " variable sign_value: integer := 1;\n";
224 m_vhdlEntry += "begin\n";
225 m_vhdlEntry += " for string_pos in decimal_string'range loop\n";
226 m_vhdlEntry += " case decimal_string(string_pos) is\n";
227 m_vhdlEntry += " when '-' => sign_value := -1;\n";
228 m_vhdlEntry += " when '0' => character_value := 0;\n";
229 m_vhdlEntry += " when '1' => character_value := 1;\n";
230 m_vhdlEntry += " when '2' => character_value := 2;\n";
231 m_vhdlEntry += " when '3' => character_value := 3;\n";
232 m_vhdlEntry += " when '4' => character_value := 4;\n";
233 m_vhdlEntry += " when '5' => character_value := 5;\n";
234 m_vhdlEntry += " when '6' => character_value := 6;\n";
235 m_vhdlEntry += " when '7' => character_value := 7;\n";
236 m_vhdlEntry += " when '8' => character_value := 8;\n";
237 m_vhdlEntry += " when '9' => character_value := 9;\n";
238 m_vhdlEntry += " when others => report(\"Illegal number\") severity failure;\n";
239 m_vhdlEntry += " end case;\n";
240 m_vhdlEntry += " tmp_signed := resize(tmp_signed * 10, wanted_bitwidth);\n";
241 m_vhdlEntry += " tmp_signed := tmp_signed + sign_value * character_value;\n";
242 m_vhdlEntry += " end loop;\n";
243 m_vhdlEntry += " return tmp_signed;\n";
244 m_vhdlEntry += "end decimal_string_to_signed;\n";
245 }
246
248}
bool m_printVhdl
Status if code should be printed.
Definition: JSignalData.h:89
std::string m_vhdlInProcess
Holds VHDL process code.
Definition: JSignalData.h:85
std::string m_vhdlOutputFile
Memebers.
Definition: JSignalData.h:79
std::string m_vhdlEntry
Holds VHDL entry code.
Definition: JSignalData.h:81
std::map< std::string, bool > m_arrayType
Holds all the required VHDL types.
Definition: JSignalData.h:98
std::map< std::string, std::vector< int > > m_buffers
vector<int> is {type, bitwidth, buffer} Holds all the requried VHDL buffers.
Definition: JSignalData.h:94
std::map< std::string, std::vector< int > > m_signals
Holds all the requried VHDL signals.
Definition: JSignalData.h:96
bool m_printedToFile
Statis if VHDL is printed to file.
Definition: JSignalData.h:91
std::string m_vhdlDefine
Holds VHDL define code.
Definition: JSignalData.h:83
std::string m_vhdlOutProcess
Holds VHDL out of process code.
Definition: JSignalData.h:87
void setPrintedToFile(bool)
Set to remember that file was printed.
Definition: JSignalData.cc:55
std::string getVhdlInProcess() const
Gets the VHDL code that are in a process statement.
Definition: JSignalData.cc:85
void printToFile()
Utilities Function to print VHDL code.
Definition: JSignalData.cc:106
std::string getVhdlOutProcess() const
Gets the VHDL code that are outside a process statement.
Definition: JSignalData.cc:90
bool getPrintVhdl() const
Gets the status of m_printVhdl.
Definition: JSignalData.cc:75
void setVhdlInProcess(const std::string &)
Set the VHDL code that are in a process statement.
Definition: JSignalData.cc:60
void setVhdlOutProcess(const std::string &)
Set the VHDL code that is outside a process statement.
Definition: JSignalData.cc:65
bool getPrintedToFile() const
Gets the status of m_printedToFile.
Definition: JSignalData.cc:80
std::map< std::string, std::vector< int > > const & getSignals() const
Gets the signals that were saved for one line of VHDL.
Definition: JSignalData.cc:100
std::string getVhdlOutputFile() const
Get the VHDL output code.
Definition: JSignalData.cc:70
std::string getVhdlDefine() const
Gets the VHDL code for define statement.
Definition: JSignalData.cc:95
void entryVhdlCode()
Function to print entry VHDL code.
Definition: JSignalData.cc:195
void signalsVhdlCode()
Function to print definition of signal VHDL code.
Definition: JSignalData.cc:178
void setVhdlOutputFile(const std::string &)
Sets the filename for VHDL output.
Definition: JSignalData.cc:45
void buffersVhdlCode()
Function to print buffer VHDL code.
Definition: JSignalData.cc:150
void setPrintVhdl(bool)
Sets if to print VHDL output.
Definition: JSignalData.cc:50
TRGCDCJSignalData()
Constructor for class.
Definition: JSignalData.cc:34
Abstract base class for different kinds of events.
STL namespace.