13#define TRGCDC_SHORT_NAMES
18#include "trg/trg/Debug.h"
19#include "trg/trg/State.h"
20#include "trg/trg/Channel.h"
21#include "trg/cdc/TRGCDC.h"
22#include "trg/cdc/Merger.h"
23#include "trg/cdc/FrontEnd.h"
24#include "trg/cdc/Wire.h"
40 :
TRGBoard(name, systemClock, dataClock, userClockOutput, userClockOutput),
45 userClockInput.
name();
55 return (
"TRGCDCMerger version 0.00");
72 outfile <<
"-- inner type" << endl;
73 string cname =
"TRGCDCMergerInner";
80 outfile <<
"--" << endl;
82 outfile <<
" component " << cname << endl;
84 outfile <<
" end component;" << endl;
86 outfile <<
"--------------------------------------------------------------"
89 outfile <<
"entity " << cname <<
"is" << endl;
91 outfile <<
"end " << cname <<
";" << endl;
93 outfile <<
"architecture Behavioral of " << cname <<
" is" << endl;
94 outfile <<
" -- local" << endl;
96 outfile <<
"begin" << endl;
97 outfile <<
"end Behavioral;" << endl;
107 outfile <<
" port (" << endl;
110 outfile <<
" -- 127.216MHz clock (TRG system clock)" << endl;
111 outfile <<
" clk : in std_logic;" << endl;
114 outfile <<
" -- Coarse timing (counter with 127.216MHz clock)" << endl;
115 outfile <<
" tmc : in std_logic_vector(0 to 7);" << endl;
118 outfile <<
" -- Hit pattern(80 bits for 80 wires)" << endl;
119 outfile <<
" ptn : in std_logic_vector(0 to 80);" << endl;
131 outfile <<
" -- Hit pattern output" << endl;
132 outfile <<
" hit : out std_logic_vector(0 to 80);" << endl;
133 outfile <<
" -- 4 bit fine timing for 16 priority wires" << endl;
134 outfile <<
" pri : out std_logic_vector(0 to 63);" << endl;
135 outfile <<
" -- 2 bit fine timing for the fastest hit in 16 TS" << endl;
136 outfile <<
" fst : out std_logic_vector(0 to 31)" << endl;
137 outfile <<
" );" << endl;
145 std::vector<const TRGCDCFrontEnd*>::push_back(a);
162 for (
unsigned i = 0; i <
_misb->size(); i++)
167 for (
unsigned i = 0; i <
_mosb->size(); i++)
177 const string ni =
name() +
"InputSignalBundle";
196 for (
unsigned s = 0; s < input1->size(); s++) {
200 for (
unsigned s = 0; s < input2->size(); s++) {
207 fedata->
clock(dClock);
208 fedata->
name(
name() +
"@dataClock");
209 _misb->push_back(fedata);
219 const string no =
name() +
"OutSigBundle";
220 if (
type() == innerType) {
225 TCMerger::packerInner);
226 }
else if (
type() == outerType) {
231 TCMerger::packerOuter);
241 output(0)->signal(
_mosb);
296 TRGState s(80 + 16 * 4 + 16 * 4 + 16 + 5 * 4 + 1 * 9 + 3);
299 bool* binput =
new bool[input.size()];
300 input.copy2bool(binput);
301 bool* binside = & binput[0];
302 bool* boutside = & binput[256];
306 const bool*
const hitptn0 = & binside[0];
307 const bool*
const hitptn1 = & boutside[0];
308 s.set(0, 32, hitptn0);
309 s.set(32, 48, hitptn1);
313 bool PTS_out_hit[16];
314 for (
unsigned i = 0; i < 16; i++) {
316 PTS_in_hit[i] = hitptn0[0] || hitptn0[16];
317 PTS_out_hit[i] = hitptn1[0] || hitptn1[1] || hitptn1[16] || hitptn1[17] || hitptn1[32] || hitptn1[33] || hitptn1[34];
319 PTS_in_hit[i] = hitptn0[1] || hitptn0[16] || hitptn0[17];
320 PTS_out_hit[i] = hitptn1[0] || hitptn1[1] || hitptn1[2] || hitptn1[16] || hitptn1[17] || hitptn1[18] || hitptn1[32] || hitptn1[33]
321 || hitptn1[34] || hitptn1[35];
322 }
else if (i == 14) {
323 PTS_in_hit[i] = hitptn0[14] || hitptn0[29] || hitptn0[30];
324 PTS_out_hit[i] = hitptn1[13] || hitptn1[14] || hitptn1[15] || hitptn1[28] || hitptn1[29] || hitptn1[30] || hitptn1[31]
325 || hitptn1[44] || hitptn1[45] || hitptn1[46] || hitptn1[47];
326 }
else if (i == 15) {
327 PTS_in_hit[i] = hitptn0[15] || hitptn0[30] || hitptn0[31];
328 PTS_out_hit[i] = hitptn1[14] || hitptn1[15] || hitptn1[29] || hitptn1[30] || hitptn1[31] || hitptn1[45] || hitptn1[46]
331 PTS_in_hit[i] = hitptn0[i] || hitptn0[i + 15] || hitptn0[i + 16];
332 PTS_out_hit[i] = hitptn1[i - 1] || hitptn1[i] || hitptn1[i + 1] || hitptn1[i + 14] || hitptn1[i + 15] || hitptn1[i + 16]
333 || hitptn1[i + 17] || hitptn1[i + 30] || hitptn1[i + 31] || hitptn1[i + 32] || hitptn1[i + 33] || hitptn1[i + 34];
339 const bool*
const pt[16] = {
340 &binside[33], &binside[38], &binside[43], &binside[48],
341 &binside[53], &binside[58], &binside[63], &binside[68],
342 &binside[73], &binside[78], &binside[83], &binside[88],
343 &binside[93], &binside[98], &binside[103], &binside[108]
346 for (
unsigned i = 0; i < 16; i++) {
352 const bool*
const ftinside[16] = {
353 &binside[128], &binside[133], &binside[138], &binside[143],
354 &binside[148], &binside[153], &binside[158], &binside[163],
355 &binside[168], &binside[173], &binside[178], &binside[183],
356 &binside[188], &binside[193], &binside[198], &binside[203]
358 const bool*
const ftoutside[16] = {
359 &boutside[48], &boutside[53], &boutside[58], &boutside[63],
360 &boutside[68], &boutside[73], &boutside[78], &boutside[83],
361 &boutside[88], &boutside[93], &boutside[98], &boutside[103],
362 &boutside[108], &boutside[113], &boutside[118], &boutside[123]
367 for (
unsigned i = 0; i < 16; i++) {
371 if (!PTS_in_hit[i]) st[0].set(5,
true);
372 if (!PTS_out_hit[i]) st[1].set(5,
true);
374 if (PTS_in_hit[i] || PTS_out_hit[i]) {
376 s.set(p, 4, &binside[129 + i * 5]);
378 s.set(p, 4, &boutside[49 + i * 5]);
386 s.set(p, 16, &binside[112]);
392 s.set(p, 4, &binside[209]);
399 s.set(p, 4, &boutside[129]);
405 if (hitptn1[0] || hitptn1[16] || hitptn1[32] || hitptn1[33]) {
406 s.set(p, 4, &boutside[134]);
415 et[1] =
TRGState(5, &boutside[138]);
417 if ((!hitptn1[15]) && (!hitptn1[30]) && (!hitptn1[31]) && (!hitptn1[46]) && (!hitptn1[47])) et[1].
set(5,
true);
418 if ((!hitptn0[31])) et[0].
set(5,
true);
420 if (hitptn0[31] || hitptn1[15] || hitptn1[30] || hitptn1[31] || hitptn1[46] || hitptn1[47]) {
422 s.set(p, 4, &binside[209]);
424 s.set(p, 4, &boutside[139]);
433 if (hitptn1[31] || hitptn1[47]) {
434 s.set(p, 4, &boutside[144]);
503 TRGState s(80 + 16 * 4 + 16 * 4 + 16 + 3 * 4 + 9 + 11);
506 bool* binput =
new bool[input.size()];
507 input.copy2bool(binput);
508 bool* binside = & binput[0];
509 bool* boutside = & binput[256];
513 const bool*
const hitptn0 = & binside[0];
514 const bool*
const hitptn1 = & boutside[0];
515 s.set(0, 48, hitptn0);
516 s.set(48, 32, hitptn1);
519 bool PTS_out_hit[16];
520 for (
unsigned i = 0; i < 16; i++) {
522 PTS_in_hit[i] = hitptn0[0] || hitptn0[1] || hitptn0[16] || hitptn0[32] ;
523 PTS_out_hit[i] = hitptn1[0] || hitptn1[16] || hitptn1[17];
524 }
else if (i == 15) {
525 PTS_in_hit[i] = hitptn0[14] || hitptn0[15] || hitptn0[30] || hitptn0[31] || hitptn0[47] ;
526 PTS_out_hit[i] = hitptn1[14] || hitptn1[15] || hitptn1[30] || hitptn1[31];
528 PTS_in_hit[i] = hitptn0[i - 1] || hitptn0[i] || hitptn0[i + 1] || hitptn0[i + 15] || hitptn0[i + 16] || hitptn0[i + 32];
529 PTS_out_hit[i] = hitptn1[i - 1] || hitptn1[i] || hitptn1[i + 15] || hitptn1[i + 16] || hitptn1[i + 17];
553 const bool dummy[6] = {
false,
false,
false,
false,
false,
true};
557 for (
unsigned i = 0; i < 16; i++) {
559 if (hitptn0[32 + i]) {
560 s.set(p, 4, &binside[49 + 5 * i]);;
566 s.set(p, 4, &boutside[49]);
568 s.set(208 + i, 1,
true);
574 st[0] =
TRGState(5, &boutside[43 + i * 5]);
575 st[1] =
TRGState(5, &boutside[48 + i * 5]);
576 if (!hitptn1[i - 1]) st[0].set(5,
true);
577 if (!hitptn1[i]) st[1].set(5,
true);
579 if (hitptn1[i] || hitptn1[i - 1]) {
581 s.set(p, 4, &boutside[49 + i * 5]);
582 s.set(208 + i, 1,
true);
585 s.set(p, 4, &boutside[44 + i * 5]);
620 for (
unsigned i = 0; i < 16; i++) {
622 st[0] =
TRGState(5, &binside[128 + i * 5]);
623 st[1] =
TRGState(5, &boutside[128 + i * 5]);
625 if (!PTS_in_hit[i]) st[0].set(5,
true);
626 if (!PTS_out_hit[i]) st[1].set(5,
true);
628 if (PTS_in_hit[i] || PTS_out_hit[i]) {
630 s.set(p, 4, &binside[129 + i * 5]);
632 s.set(p, 4, &boutside[129 + i * 5]);
656 s.set(p, 4, &boutside[124]);
659 for (
unsigned i = 0; i < 2; i++) {
662 et[0] =
TRGState(5, &binside[208 + i * 5]);
663 et[1] =
TRGState(5, &boutside[208 + i * 5]);
666 if (!hitptn0[0]) et[0].
set(5,
true);
667 if (!hitptn1[16]) et[1].
set(5,
true);
669 if (hitptn0[0] || hitptn1[16]) {
671 s.set(p, 4, &binside[209 + i * 5]);
673 s.set(p, 4, &boutside[209 + i * 5]);
679 if (!hitptn0[15] && !hitptn0[31]) et[0].
set(5,
true);
680 if (!hitptn1[15] && !hitptn1[31]) et[1].
set(5,
true);
682 if (hitptn0[15] || hitptn0[31] || hitptn1[15] || hitptn1[31]) {
684 s.set(p, 4, &binside[209 + i * 5]);
686 s.set(p, 4, &boutside[209 + i * 5]);
726 unsigned ipos = 0, o = 0;
728 cout <<
"======================= Merger unpackerInner ================================= " << endl;
729 cout <<
"input bit information: " << endl;
730 for (
unsigned bi = 0; bi < input.size(); bi++) {
731 if (input[bi]) cout <<
"* " ;
733 if ((bi % 16) == 15) cout << endl;
734 if (bi == 255) cout <<
"--------------------------------" << endl;
737 cout <<
"Input bit size = " << input.size() <<
" and Output bit size =" << output.size() << endl << endl;
739 cout <<
"Hit map: " << endl;
740 cout <<
"inputOutside : wire hit pattern" << endl;
742 for (
unsigned i = 0; i < 48; i++) {
743 const unsigned j = 47 - i;
744 if (i && ((i % 8) == 0))
752 cout <<
"inputInside : wire hit pattern" << endl;
754 for (
unsigned i = 0; i < 32; i++) {
755 const unsigned j = 31 - i;
756 if (i && ((i % 8) == 0))
764 cout <<
"-------------------------------------------" << endl;
765 cout <<
"Output : wire hit pattern" << endl;
767 for (
unsigned i = 0; i < 80; i++) {
768 const unsigned j = 79 - i;
771 if (
int(i / 16) % 2) {
780 cout <<
" -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-" << endl << endl;
782 cout <<
"Priority cell timing:" << endl;
783 cout <<
"inputOutside : no priority cell timing information" << endl;
784 cout <<
"inputInside : priority cell timing" << endl;
786 for (
unsigned i = 0; i < 16; i++) {
790 cout << setw(2) << i <<
": " << s <<
" ";
794 cout <<
"inputInsidepriority cell location flag" << endl;
796 for (
unsigned i = 0; i < 16; i++) {
799 if (inputInside[ipos + i])
800 cout << setw(2) << i <<
": (1)Left ";
802 cout << setw(2) << i <<
": (0)Right ";
807 cout <<
"ouput : priority cell timing" << endl;
809 for (
unsigned i = 0; i < 16; i++) {
810 TRGState s = output.subset(o + i * 4, 4);
813 cout << setw(2) << i <<
": " << s <<
" ";
817 cout <<
"output : priority cell location flag" << endl;
819 for (
unsigned i = 0; i < 16; i++) {
823 cout << setw(2) << i <<
": (1)Left ";
825 cout << setw(2) << i <<
": (0)Right ";
829 cout <<
" -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
831 cout <<
"Fastest timing of each TrackSegment: " << endl;
832 cout <<
"inputOutside : fastest timing" << endl;
834 for (
unsigned i = 0; i < 16; i++) {
838 cout << setw(2) << i <<
": " << s <<
" ";
843 cout <<
"inputInside : fastest timing" << endl;
844 for (
unsigned i = 0; i < 16; i++) {
848 cout << setw(2) << i <<
": " << s <<
" ";
852 cout <<
"output : fastest timing" << endl;
854 for (
unsigned i = 0; i < 16; i++) {
855 TRGState s = output.subset(o + i * 4, 4);
858 cout << setw(2) << i <<
": " << s <<
" ";
862 cout <<
" -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
864 cout <<
"Edge time information: " << endl;
865 cout <<
"inputOutside : timing of missing wires" << endl;
867 for (
unsigned i = 0; i < 4; i++) {
871 cout << setw(2) << i <<
": " << s <<
" ";
876 cout <<
"inputInside : timing of missing wires" << endl;
877 for (
unsigned i = 0; i < 1; i++) {
881 cout << setw(2) << i <<
": " << s <<
" ";
885 cout <<
"output : timing of missing wires" << endl;
887 for (
unsigned i = 0; i < 5; i++) {
888 TRGState s = output.subset(o + i * 4, 4);
891 cout << setw(2) << i <<
": " << s <<
" ";
897 cout <<
"================== End of Merger unpackerInner ========================= " << endl;
914 cout <<
"======================= Merger unpackerOuter================================== " << endl;
915 cout <<
"input bit information: " << endl;
916 for (
unsigned bi = 0; bi < input.size(); bi++) {
917 if (input[bi]) cout <<
"* " ;
919 if ((bi % 16) == 15) cout << endl;
920 if (bi == 255) cout <<
"--------------------------------" << endl;
923 cout <<
"Input bit size = " << input.size() <<
" and Output bit size =" << output.size() << endl << endl;
925 cout <<
"Hit map: " << endl;
926 cout <<
"inputOutside : wire hit pattern" << endl;
928 for (
unsigned i = 0; i < 48; i++) {
929 const unsigned j = 47 - i;
930 if (i && ((i % 8) == 0))
938 cout <<
"inputInside : wire hit pattern" << endl;
940 for (
unsigned i = 0; i < 48; i++) {
941 const unsigned j = 48 - i - 1;
942 if (i && ((i % 8) == 0))
950 cout <<
"-------------------------------------------" << endl;
951 cout <<
"Output : wire hit pattern" << endl;
953 for (
unsigned i = 0; i < 80; i++) {
954 const unsigned j = 79 - i;
966 if (
int(i / 16) % 2) {
976 cout <<
" -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-" << endl << endl;
978 cout <<
"Priority cell timing:" << endl;
979 cout <<
"inputOutside : priority cell timing" << endl;
981 for (
unsigned i = 0; i < 16; i++) {
985 cout << setw(2) << i <<
": " << s <<
" ";
989 cout <<
"inputInside : priority cell timing" << endl;
990 for (
unsigned i = 0; i < 16; i++) {
994 cout << setw(2) << i <<
": " << s <<
" ";
998 cout <<
"ouput : priority cell timing" << endl;
1000 for (
unsigned i = 0; i < 16; i++) {
1001 TRGState s = output.subset(o + i * 4, 4);
1004 cout << setw(2) << i <<
": " << s <<
" ";
1008 cout <<
"output : priority cell location flag" << endl;
1010 for (
unsigned i = 0; i < 16; i++) {
1014 cout << setw(2) << i <<
": (1)Left ";
1016 cout << setw(2) << i <<
": (0)Right ";
1020 cout <<
" -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
1022 cout <<
"Fastest timing of each TrackSegment: " << endl;
1023 cout <<
"inputOutside : fastest timing" << endl;
1025 for (
unsigned i = 0; i < 16; i++) {
1029 cout << setw(2) << i <<
": " << s <<
" ";
1033 cout <<
"inputInside : fastest timing" << endl;
1034 for (
unsigned i = 0; i < 16; i++) {
1038 cout << setw(2) << i <<
": " << s <<
" ";
1042 cout <<
"output : fastest timing" << endl;
1044 for (
unsigned i = 0; i < 16; i++) {
1045 TRGState s = output.subset(o + i * 4, 4);
1048 cout << setw(2) << i <<
": " << s <<
" ";
1052 cout <<
" -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
1054 cout <<
"Edge time information: " << endl;
1055 cout <<
"inputOutside : timing of missing wires" << endl;
1057 for (
unsigned i = 0; i < 2; i++) {
1061 cout << setw(2) << i <<
": " << s <<
" ";
1065 cout <<
"inputInside : timing of missing wires" << endl;
1066 for (
unsigned i = 0; i < 2; i++) {
1070 cout << setw(2) << i <<
": " << s <<
" ";
1074 cout <<
"output : timing of missing wires" << endl;
1076 for (
unsigned i = 0; i < 3; i++) {
1077 TRGState s = output.subset(o + i * 4, 4);
1080 cout << setw(2) << i <<
": " << s <<
" ";
1086 cout <<
"================= End of Merger unpackerOuter ========================= " << endl;
1094 if (
type() == innerType) {
1106 ofstream output((
name() +
".log").c_str());
1108 output <<
"Inner Superlayer Merger output dump" << endl << endl;
1111 std::vector<vector<int>> boolvector(changetime.size());
1112 for (
unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1114 for (
unsigned b = 0; b < (* _mosb)[0]->size(); b++) {
1115 boolvector[ch_t].push_back(((*
_mosb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1118 output <<
"# of clk: " << changetime[ch_t] <<
" (" << dClock.
absoluteTime(changetime[ch_t]) <<
" ns), signal vector: " << endl;
1120 output <<
"Hitmap: " << endl <<
" ";
1121 for (
int b = 0; b < 80; b++) {
1122 output << boolvector[ch_t][79 - b] <<
" ";
1123 if (b == 15) output << endl;
1124 else if (b == 31) output << endl <<
" ";
1125 else if (b == 47) output << endl ;
1126 else if (b == 63) output << endl <<
" ";
1130 for (
int b = 0; b < 16; b++) {
1131 output <<
"PT#" << b <<
": " << boolvector[ch_t][ 80 + 4 * b + 3 ] << boolvector[ch_t][ 80 + 4 * b + 2 ] << boolvector[ch_t][ 80 + 4
1133 << boolvector[ch_t][ 80 + 4 * b ] << endl;
1137 for (
int b = 0; b < 16; b++) {
1138 output <<
"FT#" << b <<
": " << boolvector[ch_t][ 144 + 4 * b + 3 ] << boolvector[ch_t][ 144 + 4 * b + 2 ] << boolvector[ch_t][ 144
1140 << boolvector[ch_t][ 144 + 4 * b ] << endl;
1143 output <<
"Secondary: " << endl;
1144 for (
int b = 0; b < 16; b++) {
1145 output << boolvector[ch_t][ 223 - b ] ;
1149 output <<
"ET#0(31): " << endl << boolvector[ch_t][227] << boolvector[ch_t][226] << boolvector[ch_t][225] << boolvector[ch_t][224]
1151 output <<
"ET#1(64(out32)): " << endl << boolvector[ch_t][231] << boolvector[ch_t][230] << boolvector[ch_t][229] <<
1152 boolvector[ch_t][228]
1154 output <<
"ET#2(32, 48, 64, 65(outside 0, 16, 32, 33)): " << endl << boolvector[ch_t][235] << boolvector[ch_t][234] <<
1155 boolvector[ch_t][233]
1156 << boolvector[ch_t][232] << endl;
1157 output <<
"ET#3(31, 47, 62, 63, 78, 79(inside 31, outside 15, 30, 31, 46, 47)): " << endl << boolvector[ch_t][239] <<
1158 boolvector[ch_t][238]
1159 << boolvector[ch_t][237] << boolvector[ch_t][236] << endl;
1160 output <<
"ET#4(63, 79(outside 31, 47)): " << endl << boolvector[ch_t][243] << boolvector[ch_t][242] << boolvector[ch_t][241]
1161 << boolvector[ch_t][240] << endl;
1177 ofstream output((
name() +
".log").c_str());
1179 output <<
"Outer Superlayer Merger output dump" << endl << endl;
1182 std::vector<vector<int>> boolvector(changetime.size());
1183 for (
unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1185 for (
unsigned b = 0; b < (* _mosb)[0]->size(); b++) {
1186 boolvector[ch_t].push_back(((*
_mosb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1189 output <<
"# of clk: " << changetime[ch_t] <<
" (" << dClock.
absoluteTime(changetime[ch_t]) <<
" ns), signal vector: " << endl;
1191 output <<
"Hitmap: " << endl <<
" ";
1192 for (
int b = 0; b < 80; b++) {
1193 output << boolvector[ch_t][79 - b] <<
" ";
1194 if (b == 15) output << endl;
1195 else if (b == 31) output << endl <<
" ";
1196 else if (b == 47) output << endl ;
1197 else if (b == 63) output << endl <<
" ";
1201 for (
int b = 0; b < 16; b++) {
1202 output <<
"PT#" << b <<
": " << boolvector[ch_t][ 80 + 4 * b + 3 ] << boolvector[ch_t][ 80 + 4 * b + 2 ] << boolvector[ch_t][ 80 + 4
1204 << boolvector[ch_t][ 80 + 4 * b ] << endl;
1208 for (
int b = 0; b < 16; b++) {
1209 output <<
"FT#" << b <<
": " << boolvector[ch_t][ 144 + 4 * b + 3 ] << boolvector[ch_t][ 144 + 4 * b + 2 ] << boolvector[ch_t][ 144
1211 << boolvector[ch_t][ 144 + 4 * b ] << endl;
1214 output <<
"Secondary: ";
1215 for (
int b = 0; b < 16; b++) {
1216 output << boolvector[ch_t][ 223 - b ] ;
1220 output <<
"ET#0(63(outside 15)): " << endl << boolvector[ch_t][227] << boolvector[ch_t][226] << boolvector[ch_t][225] <<
1221 boolvector[ch_t][224]
1223 output <<
"ET#1(0,64(inside 0, out 16)): " << endl << boolvector[ch_t][231] << boolvector[ch_t][230] << boolvector[ch_t][229]
1224 << boolvector[ch_t][228] << endl;
1225 output <<
"ET#2(15,31,63,79(inside 15, 31, outside 15, 31)): " << endl << boolvector[ch_t][235] << boolvector[ch_t][234]
1226 << boolvector[ch_t][233] << boolvector[ch_t][232] << endl;
A class to represent a trigger board.
A class to represent a CDC front-end board.
TRGSignalBundle * _mosb
outptu signal bundle
TRGSignalBundle * _misb
Input single bundle.
TRGSignalBundle * mosb
Output signal bundle. not the best way to do this though.
A class to represent a digitized signal. Unit is nano second.
A class to represent a bundle of SignalVectors.
A class to represent a bundle of digitized signals.
A class to represent a digitized signal. Unit is nano second.
A class to represent a state of multi bits.
static std::string tab(void)
returns tab spaces.
static TRGCDC * getTRGCDC(void)
returns TRGCDC object.
double absoluteTime(int clockPosition) const
returns absolute time of clock position
static int implementation(const unitType &type, std::ofstream &)
make a VHDL component file.
TRGState subset(unsigned i, unsigned n) const
returns subset from i with n bits.
static void unpackerOuter(const TRGState &input, const TRGState &output)
Unpack TRGState.
const TRGClock & clock(void) const
returns clock.
const TRGClock & clockData(void) const
returns data clock.
void dump_log_outer(void) const
dump_log for outer Merger
static int implementationPort(const unitType &type, std::ofstream &)
writes a port map.
const std::string & name(void) const
returns name.
static TRGState packerInner(const TRGState &input)
Make bit pattern using input information from inner FEs.
std::vector< int > stateChanges(void) const
returns a list of clock position of state change.
static void enterStage(const std::string &stageName)
Declare that you enter new stage.
void dump_log(void) const
Dump all the details of _mosb into a .log file, do it in the end of simulate()
unitType type(void) const
return type.
const TRGState & set(unsigned position, bool state=true)
sets state at bit i.
const TRGClock & dataClock(void) const
returns the data clock.
virtual ~TRGCDCMerger()
Destructor.
TRGCDCMerger(const std::string &name, unitType type, const TRGClock &systemClock, const TRGClock &dataClock, const TRGClock &userClockInput, const TRGClock &userClockOutput)
Constructor.
static TRGState packerOuter(const TRGState &input)
Make bit pattern using input information from outer FEs.
static int level(void)
returns the debug level.
void dump_log_inner(void) const
dump_log for inner Merger
static void leaveStage(const std::string &stageName)
Declare that you leave a stage.
static std::string version(void)
return version.
void dumpCOE(const std::string &fileName="", int start=0, int stop=0) const
makes coe output.
void simulate(void)
simulates firmware.
void push_back(const TRGCDCFrontEnd *)
push back TRGCDCFrontEnd of this Merger
static void unpackerInner(const TRGState &input, const TRGState &output)
Unpack TRGState.
void dump(const std::string &message="", const std::string &pre="") const
dumps contents. "message" is to select information to dump. "pre" will be printed in head of each lin...
Abstract base class for different kinds of events.