15#include "trg/trg/Utilities.h"
20#define NAME "HoughMapping"
21#define VERSION "version 0.01"
38void printHeader(ofstream& out,
const string& function);
39void superLayer(
const unsigned id);
40void printMapping(ofstream& out, vector<vector<vector<int>>>& HPcell);
44const double PI2 = 2 * M_PI;
46const double minY = 1.823908740944321;
47const double maxY = 3.204119982655926;
49const unsigned nX = 160;
50const unsigned nY = 16;
52vector<vector<vector<int>>> HPcellM(nY, vector<vector<int>>(nX, vector<int>()));
53ofstream outputM(
"minus_total.dat");
55vector<vector<vector<int>>> HPcellP(nY, vector<vector<int>>(nX, vector<int>()));
56ofstream outputP(
"plus_total.dat");
60const string fncM =
"HoughMappingMinus.cc";
61const string fncP =
"HoughMappingPlus.cc";
68 cout << NAME <<
" ... " << VERSION << endl;
70 printHeader(outcM,
"HoughMappingMinus");
71 printHeader(outcP,
"HoughMappingPlus");
73 for (
unsigned isl = 0; isl < 5 ; isl++)
76 printMapping(outputM, HPcellM);
77 printMapping(outputP, HPcellP);
79 outcM << endl <<
"}" << endl;
80 outcP << endl <<
"}" << endl;
86 cout <<
"Files generated" << endl;
87 cout <<
" c++ for tsim firmware : " << fncM << endl;
88 cout <<
" c++ for tsim firmware : " << fncP << endl;
92printHeader(ofstream& out,
const string& function)
95 string ts = TRGUtil::dateString();
97 out <<
"// This file is generated by " << NAME <<
"(" << VERSION <<
")" << endl;
98 out <<
"// " << ts << endl << endl;
99 out <<
"#define TRGCDC_SHORT_NAMES" << endl;
100 out <<
"#include \"trg/trg/State.h\"" << endl;
101 out <<
"#include \"trg/cdc/Tracker2D.h\"" << endl;
102 out <<
"using namespace std;" << endl;
103 out <<
"using namespace Belle2;" << endl;
104 out <<
"void" << endl;
105 out <<
"TCTracker2D::" << function <<
"(void) {" << endl;
107 out <<
" //...TS hit map..." << endl;
108 out <<
" TRGState SL0_TS = _ts.subset(0, 160);" << endl;
109 out <<
" TRGState SL2_TS = _ts.subset(160, 192);" << endl;
110 out <<
" TRGState SL4_TS = _ts.subset(160 + 192, 256);" << endl;
111 out <<
" TRGState SL6_TS = _ts.subset(160 + 192 + 256, 320);" << endl;
112 out <<
" TRGState SL8_TS = _ts.subset(160 + 192 + 256 + 320, 384);" << endl;
114 out <<
" //...Hough cells..." << endl;
116 for (
unsigned isl = 0; isl < 5; isl++) {
117 for (
unsigned iy = 1; iy < nY + 1; iy++) {
118 out <<
" TRGState SL" << to_string(isl * 2) <<
"_row"
119 << to_string(iy) <<
"(" << to_string(nX) <<
");" << endl;
125superLayer(
const unsigned id)
136 }
else if (
id == 1) {
139 }
else if (
id == 2) {
142 }
else if (
id == 3) {
145 }
else if (
id == 4) {
149 cout << NAME <<
" !!! bad super layer ID" << endl;
159 for (
int i = 0; i < N_TS_SL; ++i) {
160 xy.
x = r_SL * cos((PI2 / N_TS_SL) * i);
161 xy.
y = r_SL * sin((PI2 / N_TS_SL) * i);
162 xymatrix.push_back(xy);
166 const double r0 = minY;
167 const double phi0 = 0;
168 const double dr = (maxY - minY) / nY;
169 const double dphi = PI2 / nX;
179 const string vhM =
"UT3_0_SL" + to_string(
id * 2) +
".vhd";
180 const string vhP =
"UT3_0_SL" + to_string(
id * 2) +
"_p.vhd";
181 ofstream outputfM(vhM);
182 ofstream outputfP(vhP);
185 outputfM <<
"library IEEE;" << endl;
186 outputfM <<
"use IEEE.STD_LOGIC_1164.ALL;" << endl;
187 outputfM <<
" " << endl;
188 outputfM <<
" " << endl;
189 outputfM <<
"entity UT3_0_SL" << SL <<
" is" << endl;
190 outputfM <<
" " << endl;
191 outputfM <<
"Port (" << endl;
192 for (
unsigned irow = 1; irow < nY + 1; ++irow) {
193 outputfM <<
" SL" << SL <<
"_row" << left << setw(2) << to_string(irow)
194 <<
" : out STD_LOGIC_VECTOR (79 downto 40);" << endl;
196 outputfM <<
" SL" << SL <<
"_TS : in STD_LOGIC_VECTOR ("
197 << N_TS_SL / 2 <<
" downto 0));" << endl;
198 outputfM <<
"end UT3_0_SL" << SL <<
";" << endl;
199 outputfM <<
" " << endl;
200 outputfM <<
" " << endl;
201 outputfM <<
"architecture Behavioral of UT3_0_SL" << SL <<
" is" << endl;
202 outputfM <<
" " << endl;
203 outputfM <<
"begin" << endl;
204 outputfM <<
" " << endl;
207 outputfP <<
"library IEEE;" << endl;
208 outputfP <<
"use IEEE.STD_LOGIC_1164.ALL;" << endl;
209 outputfP <<
" " << endl;
210 outputfP <<
" " << endl;
211 outputfP <<
"entity UT3_0_SL" << SL <<
"_P is" << endl;
212 outputfP <<
" " << endl;
213 outputfP <<
"Port (" << endl;
214 for (
unsigned irow = 1; irow < nY + 1; ++irow) {
215 outputfP <<
" SL" << SL <<
"_row" << left << setw(2) << to_string(irow)
216 <<
" : out STD_LOGIC_VECTOR (39 downto 0);" << endl;
218 outputfP <<
" SL" << SL <<
"_TS : in STD_LOGIC_VECTOR ("
219 << N_TS_SL / 2 <<
" downto 0));" << endl;
220 outputfP <<
"end UT3_0_SL" << SL <<
"_P;" << endl;
221 outputfP <<
" " << endl;
222 outputfP <<
" " << endl;
223 outputfP <<
"architecture Behavioral of UT3_0_SL" << SL <<
"_P is" << endl;
224 outputfP <<
" " << endl;
225 outputfP <<
"begin" << endl;
226 outputfP <<
" " << endl;
229 for (
unsigned k = 0 ; k < nY ; ++k) {
231 for (
unsigned j = 0 ; j < nX ; ++j) {
235 if (j > 39 && j < 80)
236 outputfM <<
"SL" << SL <<
"_row" << k + 1 <<
"(" << j <<
")<=";
238 outputfP <<
"SL" << SL <<
"_row" << k + 1 <<
"(" << j <<
")<=";
239 outcM <<
" SL" << SL <<
"_row" << k + 1 <<
".set(" << j <<
", ";
240 outcP <<
" SL" << SL <<
"_row" << k + 1 <<
".set(" << j <<
", ";
244 phi1 = phi0 + j * dphi;
245 phi2 = phi0 + (j + 1) * dphi;
248 for (
int i = 0 ; i < N_TS_SL ; i++) {
250 r1 = ((xymatrix[i].x * xymatrix[i].x) + (xymatrix[i].y * xymatrix[i].y)) /
251 ((2 * xymatrix[i].x * cos(phi1)) + (2 * xymatrix[i].y * sin(phi1)));
252 r2 = ((xymatrix[i].x * xymatrix[i].x) + (xymatrix[i].y * xymatrix[i].y)) /
253 ((2 * xymatrix[i].x * cos(phi2)) + (2 * xymatrix[i].y * sin(phi2)));
270 if (r1 > 0 && r2 > 0 && r1 < r2) {
274 minus1 = r0 + (k + 1) * dr - log10(r1);
275 minus2 = r0 + k * dr - log10(r2);
276 if (minus1 * minus2 <= 0.0) {
277 HPcellM[k][j].push_back(SL);
278 HPcellM[k][j].push_back(i);
284 if (j > 39 && j < 80)
289 if (j > 39 && j < 80)
290 outputfM <<
"SL" << SL <<
"_TS(" << i <<
") ";
292 outcM <<
"SL" << SL <<
"_TS[" << i <<
"]";
295 }
else if (r2 < 0 && r1 > 0) {
299 minus1 = r0 + (k + 1) * dr - log10(r1);
301 HPcellM[k][j].push_back(SL);
302 HPcellM[k][j].push_back(i);
308 if (j > 39 && j < 80)
312 if (j > 39 && j < 80)
313 outputfM <<
"SL" << SL <<
"_TS(" << i <<
") ";
315 outcM <<
"SL" << SL <<
"_TS[" << i <<
"]";
321 if (r1 > 0 && r2 > 0 && r2 < r1) {
325 plus1 = r0 + (k + 1) * dr - log10(r2);
326 plus2 = r0 + k * dr - log10(r1);
327 if (plus1 * plus2 <= 0.0) {
328 HPcellP[k][j].push_back(SL);
329 HPcellP[k][j].push_back(i);
339 outputfP <<
"SL" << SL <<
"_TS(" << i <<
") ";
341 outcP <<
"SL" << SL <<
"_TS[" << i <<
"]";
344 }
else if (r1 < 0 && r2 > 0) {
348 plus1 = r0 + (k + 1) * dr - log10(r2);
350 HPcellP[k][j].push_back(SL);
351 HPcellP[k][j].push_back(i);
361 outputfP <<
"SL" << SL <<
"_TS(" << i <<
") ";
363 outcP <<
"SL" << SL <<
"_TS[" << i <<
"]";
369 if (j > 39 && j < 80)
370 outputfM <<
";" << endl;
372 outputfP <<
";" << endl;
373 outcM <<
");" << endl;
374 outcP <<
");" << endl;
377 outputfM <<
" " << endl;
378 outputfM <<
"end Behavioral;" << endl;
379 outputfP <<
" " << endl;
380 outputfP <<
"end Behavioral;" << endl;
385printMapping(ofstream& out, vector<vector<vector<int>>>& HPcell)
388 string ts = TRGUtil::dateString();
389 out <<
"// This file is generated by " << NAME <<
"(" << VERSION <<
")" << endl;
390 out <<
"// " << ts << endl << endl;
392 out << nX <<
" " << nY <<
" " << minY <<
" " << maxY << endl;
394 for (
unsigned iy = 0; iy < nY; iy++) {
395 for (
unsigned ix = 0; ix < nX; ix++) {
396 out << ix <<
" " << iy + 1 <<
" ";
397 for (
unsigned its = 0; its < HPcell[iy][ix].size(); its++) {
398 out << HPcell[iy][ix][its] <<
" ";
Abstract base class for different kinds of events.