Belle II Software development
TRGGDL.h
1/**************************************************************************
2 * basf2 (Belle II Analysis Software Framework) *
3 * Author: The Belle II Collaboration *
4 * *
5 * See git log for contributors and copyright holders. *
6 * This file is licensed under LGPL-3.0, see LICENSE.md. *
7 **************************************************************************/
8
9#ifndef TRGGDL_FLAG_
10#define TRGGDL_FLAG_
11
12#define TRGGDL_UNDEFINED 999999
13
14#include <fstream>
15#include <vector>
16#include "trg/trg/Clock.h"
17#include "trg/trg/SignalVector.h"
18#include "trg/trg/SignalBundle.h"
19
20#include <framework/database/DBObjPtr.h>
21#include <mdst/dbobjects/TRGGDLDBInputBits.h>
22#include <mdst/dbobjects/TRGGDLDBFTDLBits.h>
23#include <mdst/dbobjects/TRGGDLDBPrescales.h>
24#include <trg/gdl/dbobjects/TRGGDLDBAlgs.h>
25#include <simulation/dataobjects/SimClockState.h>
26#include <framework/dbobjects/HardwareClockSettings.h>
27#include <TH1I.h>
28
29namespace Belle2 {
35 class TRGClock;
36 class TRGLink;
37
43
44 class TRGGDL {
45
46 public:
47
49 static TRGGDL* getTRGGDL(const std::string& configFile,
50 unsigned simulationMode = 0,
51 unsigned fastSimulationMode = 0,
52 unsigned firmwareSimulationMode = 0,
53 const std::string& Phase = "Phase",
54 bool algFromDB = true,
55 const std::string& algFilePath = "ftd.alg",
56 int debugLevel = 0,
57 double timquality_threshold_sfin = 0,
58 double timquality_threshold_fine = 0);
59
62 static TRGGDL* getTRGGDL(void);
63
64 private:
65
67 TRGGDL(const std::string& configFile,
68 unsigned simulationMode,
69 unsigned fastSimulationMode,
71 const std::string& Phase,
72 bool algFromDB = true,
73 const std::string& algFilePath = "ftd.alg",
74 int debugLevel = 0,
75 double timquality_threshold_sfin = 0,
76 double timquality_threshold_fine = 0);
77
79 virtual ~TRGGDL();
80
82 void initialize(void);
83
85 void configure(void);
86
88 void simulate(void);
89
91 void terminate(void);
92
93 public:// Selectors
94
96 std::string name(void) const;
97
99 std::string version(void) const;
100
102 std::string configFile(void) const;
103
105 unsigned mode(void) const;
106
108 unsigned mode(unsigned);
109
111 unsigned firmwareSimulationMode(void) const;
112
114 void dump(const std::string& message) const;
115
117 int debugLevel(void) const;
118
120 int debugLevel(int) const;
121
122 public:// Event by event information.
123
125 void clear(void);
126
128 void fastClear(void);
129
131 void update(bool mcAnalysis = true);
132
133 public:
134
136 const TRGClock& systemClock(void) const;
137
139 double systemOffsetMC(void) const;
140
142 static TRGState decision(const TRGState& input);
143
145 static void (* _ftd)(bool* out, const bool* in);
146
148 static TRGState timingDecision(const TRGState& input,
149 TRGState& registers,
150 bool& logicStillActive);
151
152 bool doprescale(int f);
153
154 bool isFiredFTDL(std::vector<bool> input, std::string alg);
155
157 void checkDatabase() const;
158
159 std::vector<bool> getInpBits(void) {return _inpBits;}
160
161 std::vector<bool> getFtdBits(void) {return _ftdBits;}
162
163 std::vector<bool> getPsnBits(void) {return _psnBits;}
164
165 private:
166
168 void updateMC(void);
169
171 void fastSimulation(void);
172
174 void firmwareSimulation(void);
175
177 void dataSimulation(void);
178
180 void getInput(std::ifstream& ifs);
181
183 void getOutput(std::ifstream& ifs);
184
186 void getAlgorithm(std::ifstream& ifs);
187
189 void accumulateInp(TH1I*);
190
192 void accumulateFtd(TH1I*);
193
195 void accumulatePsn(TH1I*);
196
198 bool isFiredInput(int n) {return _inpBits[n];}
199
201 bool isFiredFtdl(int n) {return _ftdBits[n];}
202
204 bool isFiredPsnm(int n) {return _psnBits[n];}
205
206 private:
207
209 static TRGGDL* _gdl;
210
212 mutable int _debugLevel;
213
215 std::string _configFilename;
216
219
222
225
226 //Phase
227 std::string _Phase;
228
229 // Path to algorithm file
230 std::string _algFilePath;
231
234
236 const double _offset;
237
239 std::vector<TRGLink*> _links;
240
242 std::vector<std::string> _input;
243
245 std::vector<std::string> _output;
246
248 std::vector<std::string> _algorithm;
249
252
255
258
261
264 DBObjPtr<TRGGDLDBFTDLBits> m_FTDLBitsDB;
265 DBObjPtr<TRGGDLDBPrescales> m_PrescalesDB;
266 DBObjPtr<TRGGDLDBAlgs> m_AlgsDB;
267
270
273
275 std::vector<bool> _inpBits;
276 std::vector<bool> _ftdBits;
277 std::vector<bool> _psnBits;
278 std::vector<std::string> _inpBitNames;
279 std::vector<std::string> _oupBitNames;
280
281 int getNbitsOup(void) {return _oupBitNames.size();}
282 int getNbitsInp(void) {return _inpBitNames.size();}
283
284 bool _algFromDB;
285
290
291
292 friend class TRGGDLModule;
293 };
294
295//-----------------------------------------------------------------------------
296
297 inline
298 int
300 {
301 return _debugLevel;
302 }
303
304 inline
305 int
307 {
308 return _debugLevel = a;
309 }
310
311 inline
312 const TRGClock&
314 {
315 return _clock;
316 }
317
318 inline
319 double
321 {
322 return _offset;
323 }
324
325 inline
326 unsigned
328 {
330 }
331
332 inline
333 std::string
335 {
336 return _configFilename;
337 }
338
339
341} // namespace Belle2
342
343#endif /* TRGGDL_FLAG_ */
Class for accessing objects in the database.
Definition: DBObjPtr.h:21
Type-safe access to single objects in the data store.
Definition: StoreObjPtr.h:96
A class to represent a digitized signal. Unit is nano second.
Definition: Clock.h:38
A module to simulate the Global Decision Logic.
Definition: TRGGDLModule.h:34
The instance of TRGGDL is a singleton.
Definition: TRGGDL.h:44
TRGSignalBundle * _isb
Input signal bundle.
Definition: TRGGDL.h:251
TRGSignalBundle * _tosb
Timing output signal bundle.
Definition: TRGGDL.h:260
const double _offset
Timing offset of GDL.
Definition: TRGGDL.h:236
unsigned _simulationMode
Simulation mode.
Definition: TRGGDL.h:218
bool isFiredFtdl(int n)
Returns fired/not for ftdl bits.
Definition: TRGGDL.h:201
std::string _configFilename
GDL configuration filename.
Definition: TRGGDL.h:215
std::vector< std::string > _algorithm
Algorithm.
Definition: TRGGDL.h:248
unsigned _fastSimulationMode
Fast simulation mode.
Definition: TRGGDL.h:221
int _debugLevel
Debug level.
Definition: TRGGDL.h:212
double _timquality_threshold_sfin
Threshold to determine timing quality flag with MC truth: super fine.
Definition: TRGGDL.h:269
bool isFiredPsnm(int n)
Returns fired/not for psnm bits.
Definition: TRGGDL.h:204
std::vector< std::string > _output
Output names.
Definition: TRGGDL.h:245
unsigned _firmwareSimulationMode
Firmware simulation mode.
Definition: TRGGDL.h:224
const TRGClock & _clock
GDL trigger system clock.
Definition: TRGGDL.h:233
std::vector< TRGLink * > _links
All serial links.
Definition: TRGGDL.h:239
unsigned mode(void) const
returns simulation mode.
unsigned mode(unsigned)
sets and returns simulation mode.
DBObjPtr< TRGGDLDBInputBits > m_InputBitsDB
Data base of GDL input bits.
Definition: TRGGDL.h:263
TRGSignalBundle * _tsb
Timing input signal bundle.
Definition: TRGGDL.h:257
DBObjPtr< HardwareClockSettings > m_hwClock
Hardware Clocks.
Definition: TRGGDL.h:289
double _timquality_threshold_fine
Threshold to determine timing quality flag with MC truth: fine.
Definition: TRGGDL.h:272
void updateMC(void)
updates TRGGDL information for MC.
std::vector< std::string > _input
Input names.
Definition: TRGGDL.h:242
TRGSignalBundle * _osb
Output signal bundle.
Definition: TRGGDL.h:254
StoreObjPtr< SimClockState > m_simClockState
generated hardware clock state
Definition: TRGGDL.h:287
bool isFiredInput(int n)
Returns fired/not for input bits.
Definition: TRGGDL.h:198
A class to represent a bundle of SignalVectors.
Definition: SignalBundle.h:26
A class to represent a state of multi bits.
Definition: State.h:24
void checkDatabase() const
Check the content of the DBObjects used by this class.
Definition: TRGGDL.cc:1001
const TRGClock & systemClock(void) const
returns the system clock.
Definition: TRGGDL.h:313
void configure(void)
configures trigger modules for firmware simulation.
Definition: TRGGDL.cc:695
int debugLevel(void) const
returns debug level.
Definition: TRGGDL.h:299
static TRGState decision(const TRGState &input)
Makes bit pattern(state) using input bit pattern(state).
Definition: TRGGDL.cc:830
static void(* _ftd)(bool *out, const bool *in)
Function to simulate final trigger decision.
Definition: TRGGDL.h:145
std::string name(void) const
returns name.
Definition: TRGGDL.cc:54
void fastClear(void)
clears TRGGDL information.
Definition: TRGGDL.cc:204
void accumulatePsn(TH1I *)
Accumulate bit info in histogram.
Definition: TRGGDL.cc:994
void terminate(void)
terminates when run is finished
Definition: TRGGDL.cc:179
static TRGGDL * getTRGGDL(void)
returns TRGGDL object.
Definition: TRGGDL.cc:103
void accumulateFtd(TH1I *)
Accumulate bit info in histogram.
Definition: TRGGDL.cc:986
static TRGGDL * _gdl
GDL singleton.
Definition: TRGGDL.h:209
void getOutput(std::ifstream &ifs)
Read output data definition.
Definition: TRGGDL.cc:776
unsigned firmwareSimulationMode(void) const
returns firmware simulation mode.
Definition: TRGGDL.h:327
void initialize(void)
initializes GDL.
Definition: TRGGDL.cc:160
void dataSimulation(void)
Data simulation.
Definition: TRGGDL.cc:360
void dump(const std::string &message) const
dumps debug information.
Definition: TRGGDL.cc:184
static TRGState timingDecision(const TRGState &input, TRGState &registers, bool &logicStillActive)
Makes timing decision.
Definition: TRGGDL.cc:870
double systemOffsetMC(void) const
returns the system offset in MC.
Definition: TRGGDL.h:320
void update(bool mcAnalysis=true)
updates TRGGDL information.
Definition: TRGGDL.cc:209
void accumulateInp(TH1I *)
Accumulate bit info in histogram.
Definition: TRGGDL.cc:978
void getAlgorithm(std::ifstream &ifs)
Read algorithm data definition.
Definition: TRGGDL.cc:801
void fastSimulation(void)
Fast simulation.
Definition: TRGGDL.cc:241
std::string version(void) const
returns version.
Definition: TRGGDL.cc:60
std::string configFile(void) const
returns configuration file name.
Definition: TRGGDL.h:334
void simulate(void)
fast trigger simulation.
Definition: TRGGDL.cc:227
void clear(void)
clears all TRGGDL information.
Definition: TRGGDL.cc:199
void firmwareSimulation(void)
Firmware simulation.
Definition: TRGGDL.cc:577
void getInput(std::ifstream &ifs)
Read input data definition.
Definition: TRGGDL.cc:752
virtual ~TRGGDL()
Destructor.
Definition: TRGGDL.cc:221
Abstract base class for different kinds of events.