12#define TRGGDL_UNDEFINED 999999
16#include "trg/trg/Clock.h"
17#include "trg/trg/SignalVector.h"
18#include "trg/trg/SignalBundle.h"
20#include <framework/database/DBObjPtr.h>
21#include <mdst/dbobjects/TRGGDLDBInputBits.h>
22#include <mdst/dbobjects/TRGGDLDBFTDLBits.h>
23#include <mdst/dbobjects/TRGGDLDBPrescales.h>
24#include <trg/gdl/dbobjects/TRGGDLDBAlgs.h>
25#include <simulation/dataobjects/SimClockState.h>
26#include <framework/dbobjects/HardwareClockSettings.h>
50 unsigned simulationMode = 0,
51 unsigned fastSimulationMode = 0,
53 const std::string& Phase =
"Phase",
54 bool algFromDB =
true,
55 const std::string& algFilePath =
"ftd.alg",
57 double timquality_threshold_sfin = 0,
58 double timquality_threshold_fine = 0);
68 unsigned simulationMode,
69 unsigned fastSimulationMode,
71 const std::string& Phase,
72 bool algFromDB =
true,
73 const std::string& algFilePath =
"ftd.alg",
75 double timquality_threshold_sfin = 0,
76 double timquality_threshold_fine = 0);
96 std::string
name(
void)
const;
99 std::string
version(
void)
const;
114 void dump(
const std::string& message)
const;
131 void update(
bool mcAnalysis =
true);
145 static void (*
_ftd)(
bool* out,
const bool* in);
150 bool& logicStillActive);
152 bool doprescale(
int f);
154 bool isFiredFTDL(std::vector<bool> input, std::string alg);
159 std::vector<bool> getInpBits(
void) {
return _inpBits;}
161 std::vector<bool> getFtdBits(
void) {
return _ftdBits;}
163 std::vector<bool> getPsnBits(
void) {
return _psnBits;}
230 std::string _algFilePath;
275 std::vector<bool> _inpBits;
276 std::vector<bool> _ftdBits;
277 std::vector<bool> _psnBits;
278 std::vector<std::string> _inpBitNames;
279 std::vector<std::string> _oupBitNames;
281 int getNbitsOup(
void) {
return _oupBitNames.size();}
282 int getNbitsInp(
void) {
return _inpBitNames.size();}
Class for accessing objects in the database.
Type-safe access to single objects in the data store.
A class to represent a digitized signal. Unit is nano second.
A module to simulate the Global Decision Logic.
The instance of TRGGDL is a singleton.
TRGSignalBundle * _isb
Input signal bundle.
TRGSignalBundle * _tosb
Timing output signal bundle.
const double _offset
Timing offset of GDL.
unsigned _simulationMode
Simulation mode.
bool isFiredFtdl(int n)
Returns fired/not for ftdl bits.
std::string _configFilename
GDL configuration filename.
std::vector< std::string > _algorithm
Algorithm.
unsigned _fastSimulationMode
Fast simulation mode.
int _debugLevel
Debug level.
double _timquality_threshold_sfin
Threshold to determine timing quality flag with MC truth: super fine.
bool isFiredPsnm(int n)
Returns fired/not for psnm bits.
std::vector< std::string > _output
Output names.
unsigned _firmwareSimulationMode
Firmware simulation mode.
const TRGClock & _clock
GDL trigger system clock.
std::vector< TRGLink * > _links
All serial links.
unsigned mode(void) const
returns simulation mode.
unsigned mode(unsigned)
sets and returns simulation mode.
DBObjPtr< TRGGDLDBInputBits > m_InputBitsDB
Data base of GDL input bits.
TRGSignalBundle * _tsb
Timing input signal bundle.
DBObjPtr< HardwareClockSettings > m_hwClock
Hardware Clocks.
double _timquality_threshold_fine
Threshold to determine timing quality flag with MC truth: fine.
void updateMC(void)
updates TRGGDL information for MC.
std::vector< std::string > _input
Input names.
TRGSignalBundle * _osb
Output signal bundle.
StoreObjPtr< SimClockState > m_simClockState
generated hardware clock state
bool isFiredInput(int n)
Returns fired/not for input bits.
A class to represent a bundle of SignalVectors.
A class to represent a state of multi bits.
void checkDatabase() const
Check the content of the DBObjects used by this class.
const TRGClock & systemClock(void) const
returns the system clock.
void configure(void)
configures trigger modules for firmware simulation.
int debugLevel(void) const
returns debug level.
static TRGState decision(const TRGState &input)
Makes bit pattern(state) using input bit pattern(state).
static void(* _ftd)(bool *out, const bool *in)
Function to simulate final trigger decision.
std::string name(void) const
returns name.
void fastClear(void)
clears TRGGDL information.
void accumulatePsn(TH1I *)
Accumulate bit info in histogram.
void terminate(void)
terminates when run is finished
static TRGGDL * getTRGGDL(void)
returns TRGGDL object.
void accumulateFtd(TH1I *)
Accumulate bit info in histogram.
static TRGGDL * _gdl
GDL singleton.
void getOutput(std::ifstream &ifs)
Read output data definition.
unsigned firmwareSimulationMode(void) const
returns firmware simulation mode.
void initialize(void)
initializes GDL.
void dataSimulation(void)
Data simulation.
void dump(const std::string &message) const
dumps debug information.
static TRGState timingDecision(const TRGState &input, TRGState ®isters, bool &logicStillActive)
Makes timing decision.
double systemOffsetMC(void) const
returns the system offset in MC.
void update(bool mcAnalysis=true)
updates TRGGDL information.
void accumulateInp(TH1I *)
Accumulate bit info in histogram.
void getAlgorithm(std::ifstream &ifs)
Read algorithm data definition.
void fastSimulation(void)
Fast simulation.
std::string version(void) const
returns version.
std::string configFile(void) const
returns configuration file name.
void simulate(void)
fast trigger simulation.
void clear(void)
clears all TRGGDL information.
void firmwareSimulation(void)
Firmware simulation.
void getInput(std::ifstream &ifs)
Read input data definition.
virtual ~TRGGDL()
Destructor.
Abstract base class for different kinds of events.