20#include <trg/gdl/modules/trggdlSummary/trggdlSummaryModule.h>
22#include <framework/datastore/StoreArray.h>
24#include <mdst/dataobjects/TRGSummary.h>
26#include <framework/database/DBObjPtr.h>
27#include <mdst/dbobjects/TRGGDLDBInputBits.h>
28#include <mdst/dbobjects/TRGGDLDBFTDLBits.h>
44 addParam(
"inputBitsWithPSNMTiming", e_inBitsWithPSNMTiming,
"List of input bits to judge triggering with the PSNM timings.", {
"passive_veto",
"cdc_veto",
"ecl_veto",
"cdcecl_veto",
"injv",
"veto"});
45 addParam(
"outputBitsWithPSNMTiming", e_outBitsWithPSNMTiming,
"List of output bits to judge triggering with the PSNM timings.", {});
51 if (
_debugLevel > 9) printf(
"TRGGDLSummaryModule::initialize() start\n");
54 for (
int i = 0; i < 320; i++) {
55 LeafBitMap[i] = m_unpacker->getLeafMap(i);
57 for (
int i = 0; i < 320; i++) {
58 strcpy(LeafNames[i], m_unpacker->getLeafnames(i));
63 for (
int i = 0; i < 10; i++) {
68 for (
int i = 0; i < 320; i++) {
69 if (strcmp(LeafNames[i],
"timtype") == 0)_e_timtype = LeafBitMap[i];
70 if (strcmp(LeafNames[i],
"rvcout") == 0) _e_rvcout = LeafBitMap[i];
71 if (strcmp(LeafNames[i],
"psn0") == 0) ee_psn[0] = LeafBitMap[i];
72 if (strcmp(LeafNames[i],
"psn1") == 0) ee_psn[1] = LeafBitMap[i];
73 if (strcmp(LeafNames[i],
"psn2") == 0) ee_psn[2] = LeafBitMap[i];
74 if (strcmp(LeafNames[i],
"psn3") == 0) ee_psn[3] = LeafBitMap[i];
75 if (strcmp(LeafNames[i],
"psn4") == 0) ee_psn[4] = LeafBitMap[i];
76 if (strcmp(LeafNames[i],
"psn5") == 0) ee_psn[5] = LeafBitMap[i];
77 if (strcmp(LeafNames[i],
"psn6") == 0) ee_psn[6] = LeafBitMap[i];
78 if (strcmp(LeafNames[i],
"psn7") == 0) ee_psn[7] = LeafBitMap[i];
79 if (strcmp(LeafNames[i],
"psn8") == 0) ee_psn[8] = LeafBitMap[i];
80 if (strcmp(LeafNames[i],
"psn9") == 0) ee_psn[9] = LeafBitMap[i];
81 if (strcmp(LeafNames[i],
"ftd0") == 0) ee_ftd[0] = LeafBitMap[i];
82 if (strcmp(LeafNames[i],
"ftd1") == 0) ee_ftd[1] = LeafBitMap[i];
83 if (strcmp(LeafNames[i],
"ftd2") == 0) ee_ftd[2] = LeafBitMap[i];
84 if (strcmp(LeafNames[i],
"ftd3") == 0) ee_ftd[3] = LeafBitMap[i];
85 if (strcmp(LeafNames[i],
"ftd4") == 0) ee_ftd[4] = LeafBitMap[i];
86 if (strcmp(LeafNames[i],
"ftd5") == 0) ee_ftd[5] = LeafBitMap[i];
87 if (strcmp(LeafNames[i],
"ftd6") == 0) ee_ftd[6] = LeafBitMap[i];
88 if (strcmp(LeafNames[i],
"ftd7") == 0) ee_ftd[7] = LeafBitMap[i];
89 if (strcmp(LeafNames[i],
"ftd8") == 0) ee_ftd[8] = LeafBitMap[i];
90 if (strcmp(LeafNames[i],
"ftd9") == 0) ee_ftd[9] = LeafBitMap[i];
91 if (strcmp(LeafNames[i],
"itd0") == 0) ee_itd[0] = LeafBitMap[i];
92 if (strcmp(LeafNames[i],
"itd1") == 0) ee_itd[1] = LeafBitMap[i];
93 if (strcmp(LeafNames[i],
"itd2") == 0) ee_itd[2] = LeafBitMap[i];
94 if (strcmp(LeafNames[i],
"itd3") == 0) ee_itd[3] = LeafBitMap[i];
95 if (strcmp(LeafNames[i],
"itd4") == 0) ee_itd[4] = LeafBitMap[i];
96 if (strcmp(LeafNames[i],
"itd5") == 0) ee_itd[5] = LeafBitMap[i];
97 if (strcmp(LeafNames[i],
"itd6") == 0) ee_itd[6] = LeafBitMap[i];
98 if (strcmp(LeafNames[i],
"itd7") == 0) ee_itd[7] = LeafBitMap[i];
99 if (strcmp(LeafNames[i],
"itd8") == 0) ee_itd[8] = LeafBitMap[i];
100 if (strcmp(LeafNames[i],
"itd9") == 0) ee_itd[9] = LeafBitMap[i];
103 maskInitialized =
false;
105 if (
_debugLevel > 9) printf(
"TRGGDLSummaryModule::initialize() end\n");
111 if (
_debugLevel > 9) printf(
"TRGGDLSummaryModule::event() start\n");
114 n_leafs = m_unpacker->getnLeafs();
115 int n_leafsExtra = 0;
116 n_leafsExtra = m_unpacker->getnLeafsExtra();
117 int n_clocks = m_unpacker->getnClks();
118 int nconf = m_unpacker->getconf();
119 int nword_input = m_unpacker->get_nword_input();
120 int nword_output = m_unpacker->get_nword_output();
123 printf(
"trggdlSummaryModule:n_leafs(%d), n_leafsExtra(%d), n_clocks(%d), nconf(%d), nword_input(%d), nword_output(%d)\n",
124 n_leafs, n_leafsExtra, n_clocks, nconf, nword_input, nword_output);
131 for (
int i = 0; i < 320; i++) {
132 if (strcmp(entAry[0]->m_unpackername[i],
"clk") == 0) clk_map = i;
135 printf(
"trggdlSummaryModule:clk_map(%d)\n", clk_map);
137 std::vector<std::vector<int> > _data(n_leafs + n_leafsExtra);
138 for (
int leaf = 0; leaf < n_leafs + n_leafsExtra; leaf++) {
139 std::vector<int> _v(n_clocks);
144 for (
int ii = 0; ii < entAry.
getEntries(); ii++) {
146 printf(
"trggdlSummaryModule:a:ii(%d)\n", ii);
147 std::vector<int*> Bits(n_leafs + n_leafsExtra);
149 for (
int i = 0; i < 320; i++) {
150 if (LeafBitMap[i] != -1) {
151 Bits[LeafBitMap[i]] = &(entAry[ii]->m_unpacker[i]);
153 printf(
"trggdlSummaryModule:ab:i(%d), LeafBitMap[i](%d), *Bits[LeafBitMap[i]](%d)\n",
154 i, LeafBitMap[i], *Bits[LeafBitMap[i]]);
157 printf(
"trggdlSummaryModule:ab:i(%d), LeafBitMap[i](%d)\n",
161 for (
int leaf = 0; leaf < n_leafs + n_leafsExtra; leaf++) {
163 printf(
"trggdlSummaryModule:ad:leaf(%d),ii(%d),clk_map(%d),*Bits[leaf](%d), entAry[ii]->m_unpacker[clk_map](%d)\n",
164 leaf, ii, clk_map, *Bits[leaf], entAry[ii]->m_unpacker[clk_map]);
165 _data[leaf][entAry[ii]->m_unpacker[clk_map]] = *Bits[leaf];
171 if (!maskInitialized) {
172 maskInitialized =
true;
174 e_inBitWPTMasks[i] = 0;
175 e_outBitWPTMasks[i] = 0;
178 for (
const auto& nowbn : e_inBitsWithPSNMTiming) {
181 nowbit =
GDLResult->getInputBitNumber(nowbn);
182 }
catch (std::invalid_argument& e) {
183 B2WARNING(
"The input bitname '" << nowbn <<
"' is not in the input bitname list! This bitname will be skipped!");
189 e_inBitWPTMasks[iWord] |= (1u << iBit);
192 for (
const auto& nowbn : e_outBitsWithPSNMTiming) {
195 nowbit =
GDLResult->getOutputBitNumber(nowbn);
196 }
catch (std::invalid_argument& e) {
197 B2WARNING(
"The output bitname '" << nowbn <<
"' is not in the FTDL bitname list! This bitname will be skipped!");
203 e_outBitWPTMasks[iWord] |= (1u << iBit);
208 GDL::EGDLTimingType gtt = (GDL::EGDLTimingType)_data[_e_timtype][0];
209 unsigned int ored = 0;
211 int psnmClk = n_clocks;
212 int l1timstart, l1timend;
224 l1timstart = n_clocks;
229 for (
int j = 0; j < (int)nword_input; j++) {
232 for (
int clk = 0; clk < n_clocks; clk++) {
234 ored |= _data[ee_itd[j]][clk];
242 for (
int clk = 0; clk < n_clocks; clk++) {
243 ored |= _data[ee_ftd[0]][clk];
248 for (
int clk = 0; clk < n_clocks; clk++) {
249 ored |= (_data[ee_ftd[2]][clk] << 16) + _data[ee_ftd[1]][clk];
254 for (
int clk = 0; clk < n_clocks; clk++) {
255 ored |= _data[ee_psn[0]][clk];
260 for (
int clk = l1timstart; ored == 0 && clk < l1timend; clk++) {
261 ored |= _data[ee_psn[0]][clk];
262 if (ored != 0) psnmClk = std::min(clk, psnmClk);
266 for (
int clk = 0; clk < n_clocks; clk++) {
267 ored |= (_data[ee_psn[2]][clk] << 16) + _data[ee_psn[1]][clk];
272 for (
int clk = l1timstart; ored == 0 && clk < l1timend; clk++) {
273 ored |= (_data[ee_psn[2]][clk] << 16) + _data[ee_psn[1]][clk];
274 if (ored != 0) psnmClk = std::min(clk, psnmClk);
277 for (
int j = 0; j < (int)nword_output; j++) {
279 for (
int clk = 0; clk < n_clocks; clk++) {
280 ored |= _data[ee_ftd[j]][clk];
285 for (
int j = 0; j < (int)nword_output; j++) {
287 for (
int clk = 0; clk < n_clocks; clk++) {
288 ored |= _data[ee_psn[j]][clk];
293 for (
int clk = l1timstart; ored == 0 && clk < l1timend; clk++) {
294 ored |= _data[ee_psn[j]][clk];
295 if (ored != 0) psnmClk = std::min(clk, psnmClk);
300 if (psnmClk <= 0) psnmClk = 1;
302 if (l1timfound && psnmClk < 32) {
303 for (
int i = 0; i < nword_input; i++) {
304 unsigned int nowmask = e_inBitWPTMasks[i];
305 if (nowmask == 0)
continue;
308 for (
int clk = psnmClk - 1; ored != 0 && clk <= psnmClk; clk++)
309 ored &= (_data[ee_itd[i]][clk] & nowmask);
311 if (ored != nowmask) {
312 unsigned int ibits =
GDLResult->getInputBits(i);
313 unsigned int result_mask = ~nowmask | ored;
314 GDLResult->setInputBits(i, ibits & result_mask);
318 for (
int i = 0; i < nword_output; i++) {
319 unsigned int nowmask = e_outBitWPTMasks[i];
320 if (nowmask == 0)
continue;
323 for (
int clk = psnmClk - 1; ored != 0 && clk <= psnmClk; clk++)
324 ored &= (_data[ee_ftd[i]][clk] & nowmask);
326 if (ored != nowmask) {
327 unsigned int fbits =
GDLResult->getFtdlBits(i);
328 unsigned int result_mask = ~nowmask | ored;
329 GDLResult->setFtdlBits(i, fbits & result_mask);
335 for (
int i = 0; i < 320; i++) {
338 GDLResult->setPreScale(bit1, bit2, m_prescales->getprescales(i));
342 if (gtt == GDL::e_tt_cdc) {
344 }
else if (gtt == GDL::e_tt_ecl) {
346 }
else if (gtt == GDL::e_tt_top) {
348 }
else if (gtt == GDL::e_tt_dphy) {
350 }
else if (gtt == GDL::e_tt_rand) {
352 }
else if (gtt == GDL::e_tt_psnm) {
359 unsigned _exp = bevt->getExperiment();
360 unsigned _run = bevt->getRun();
361 unsigned exprun = _exp * 1000000 + _run;
362 if (exprun < 13000500) {
363 GDLResult->setTimQuality(TRGSummary::TTYQ_CORS);
365 int rvcout = _data[_e_rvcout][0];
366 int q = (rvcout >> 1) & 3;
370 timQuality = TRGSummary::TTYQ_CORS;
373 timQuality = TRGSummary::TTYQ_FINE;
376 timQuality = TRGSummary::TTYQ_SFIN;
379 timQuality = TRGSummary::TTYQ_NONE;
385 if (exprun > 16000271) {
387 int i_poissonin =
GDLResult->getInputBitNumber(std::string(
"poissonin"));
390 int i_veto =
GDLResult->getInputBitNumber(std::string(
"veto"));
393 for (
int clk = 5; clk < n_clocks - 5; clk++) {
394 if ((1 << k_poissonin) & _data[ee_itd[j_poissonin]][clk]) {
396 if ((1 << k_veto) & _data[ee_itd[j_veto]][clk]) {
void setDescription(const std::string &description)
Sets the description of the module.
void setPropertyFlags(unsigned int propertyFlags)
Sets the flags for the module properties.
@ c_ParallelProcessingCertified
This module can be run in parallel processing mode safely (All I/O must be done through the data stor...
Accessor to arrays stored in the data store.
int getEntries() const
Get the number of objects in the array.
Type-safe access to single objects in the data store.
int _debugLevel
Debug Level.
virtual void initialize() override
initialize
virtual void event() override
Event.
TRGGDLSummaryModule()
Constructor.
StoreObjPtr< TRGSummary > GDLResult
output for TRGSummary
static const unsigned int c_trgWordSize
size of a l1 trigger word
ETimingType
types of trigger timing source defined in b2tt firmware
@ TTYP_DPHY
delayed physics events for background
@ TTYP_SELF
events triggered by self trigger
@ TTYP_POIS
poisson random trigger
@ TTYP_NONE
reserved (not defined yet)
@ TTYP_TOP
events triggered by TOP timing
@ TTYP_CDC
events triggered by CDC timing
@ TTYP_ECL
events triggered by ECL timing
@ TTYP_RAND
random trigger events
static const unsigned int c_ntrgWords
number of l1 trigger words
ETimingQuality
trigger timing type quality
void addParam(const std::string &name, T ¶mVariable, const std::string &description, const T &defaultValue)
Adds a new parameter to the module.
#define REG_MODULE(moduleName)
Register the given module (without 'Module' suffix) with the framework.
Abstract base class for different kinds of events.