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Belle II Software
release-05-02-19
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17 #define TRGGDL_UNDEFINED 999999
21 #include "trg/trg/Clock.h"
22 #include "trg/trg/SignalVector.h"
23 #include "trg/trg/SignalBundle.h"
25 #include <framework/database/DBObjPtr.h>
26 #include <mdst/dbobjects/TRGGDLDBInputBits.h>
27 #include <mdst/dbobjects/TRGGDLDBFTDLBits.h>
28 #include <mdst/dbobjects/TRGGDLDBPrescales.h>
29 #include <trg/gdl/dbobjects/TRGGDLDBAlgs.h>
54 unsigned simulationMode = 0,
55 unsigned fastSimulationMode = 0,
57 const std::string& Phase =
"Phase",
58 bool algFromDB =
true,
59 const std::string& algFilePath =
"ftd.alg",
70 unsigned simulationMode,
71 unsigned fastSimulationMode,
73 const std::string& Phase,
74 bool algFromDB =
true,
75 const std::string& algFilePath =
"ftd.alg",
96 std::string
name(
void)
const;
99 std::string
version(
void)
const;
105 unsigned mode(
void)
const;
108 unsigned mode(
unsigned);
114 void dump(
const std::string& message)
const;
131 void update(
bool mcAnalysis =
true);
145 static void (*
_ftd)(
bool* out,
bool* in);
150 bool& logicStillActive);
151 bool doprescale(
int f);
153 bool isFiredFTDL(std::vector<bool> input, std::string alg);
155 std::vector<bool> getInpBits(
void) {
return _inpBits;}
157 std::vector<bool> getFtdBits(
void) {
return _ftdBits;}
159 std::vector<bool> getPsnBits(
void) {
return _psnBits;}
226 std::string _algFilePath;
265 std::vector<bool> _inpBits;
266 std::vector<bool> _ftdBits;
267 std::vector<bool> _psnBits;
268 std::vector<std::string> _inpBitNames;
269 std::vector<std::string> _oupBitNames;
271 int getNbitsOup(
void) {
return _oupBitNames.size();}
272 int getNbitsInp(
void) {
return _inpBitNames.size();}
276 friend class TRGGDLModule;
void getInput(std::ifstream &ifs)
Read input data definition.
bool isFiredFtdl(int n)
Returns fired/not for ftdl bits.
unsigned firmwareSimulationMode(void) const
returns firmware simulation mode.
void getAlgorithm(std::ifstream &ifs)
Read algorithm data definition.
unsigned _firmwareSimulationMode
Firmware simulation mode.
std::string configFile(void) const
returns configuration file name.
std::vector< std::string > _input
Input names.
static TRGState decision(const TRGState &input)
Makes bit pattern(state) using input bit pattern(state).
void firmwareSimulation(void)
Firmware simulation.
double systemOffsetMC(void) const
returns the system offset in MC.
void getOutput(std::ifstream &ifs)
Read output data definition.
void accumulatePsn(TH1I *)
Accumulate bit info in histogram.
void accumulateInp(TH1I *)
Accumulate bit info in histogram.
std::string _configFilename
GDL configuration filename.
void dataSimulation(void)
Data simulation.
unsigned _fastSimulationMode
Fast simulation mode.
void dump(const std::string &message) const
dumps debug information.
void simulate(void)
fast trigger simulation.
unsigned mode(void) const
returns simulation mode.
void fastClear(void)
clears TRGGDL information.
A class to represent a state of multi bits.
TRGSignalBundle * _tsb
Timing input signal bundle.
The instance of TRGGDL is a singleton.
std::string name(void) const
returns name.
static void(* _ftd)(bool *out, bool *in)
Function to simulate final trigger decision.
std::vector< std::string > _algorithm
Algorithm.
A class to represent a bundle of SignalVectors.
std::vector< std::string > _output
Output names.
TRGSignalBundle * _osb
Output signal bundle.
virtual ~TRGGDL()
Destructor.
void updateMC(void)
updates TRGGDL information for MC.
Class for accessing objects in the database.
int debugLevel(void) const
returns debug level.
void update(bool mcAnalysis=true)
updates TRGGDL information.
static TRGState timingDecision(const TRGState &input, TRGState ®isters, bool &logicStillActive)
Makes timing decision.
int _debugLevel
Debug level.
std::vector< TRGLink * > _links
All serial links.
Abstract base class for different kinds of events.
const TRGClock & systemClock(void) const
returns the system clock.
const double _offset
Timing offset of GDL.
const TRGClock & _clock
GDL trigger system clock.
std::string version(void) const
returns version.
static TRGGDL * _gdl
GDL singleton.
TRGGDL(const std::string &configFile, unsigned simulationMode, unsigned fastSimulationMode, unsigned firmwareSimulationMode, const std::string &Phase, bool algFromDB=true, const std::string &algFilePath="ftd.alg", int debugLevel=0)
Constructor.
TRGSignalBundle * _tosb
Timing output signal bundle.
static TRGGDL * getTRGGDL(void)
returns TRGGDL object.
void accumulateFtd(TH1I *)
Accumulate bit info in histogram.
void clear(void)
clears all TRGGDL information.
void fastSimulation(void)
Fast simulation.
void terminate(void)
terminates when run is finished
unsigned _simulationMode
Simulation mode.
bool isFiredInput(int n)
Returns fired/not for input bits.
void configure(void)
configures trigger modules for firmware simulation.
DBObjPtr< TRGGDLDBInputBits > m_InputBitsDB
Data base of GDL input bits.
TRGSignalBundle * _isb
Input signal bundle.
A class to represent a digitized signal. Unit is nano second.
bool isFiredPsnm(int n)
Returns fired/not for psnm bits.
void initialize(void)
initializes GDL.