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Belle II Software
release-08-02-04
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A class to represent a serial link between trigger modules. More...
#include <OpticalLinkFrontEnd.h>


Public Member Functions | |
| TRGOpticalLinkFrontEnd (const std::string &name, const TRGClock &) | |
| Constructor. | |
| virtual | ~TRGOpticalLinkFrontEnd () |
| Destructor. | |
| const std::string & | name (void) const |
| returns name. | |
| const TRGClock & | clock (void) const |
| returns clock. | |
| void | dump (const std::string &message="", const std::string &pre="") const |
| dumps contents. More... | |
| void | appendHeader (const TRGSignal *) |
| appends a signal to header data. | |
| void | appendTrailer (const TRGSignal *) |
| appends a signal to trailer data. | |
| void | append (const TRGSignal *) |
| appends a signal to data. | |
Private Attributes | |
| const TRGSignal * | _hit |
| VHDL : begin. More... | |
| std::vector< const TRGSignal * > | _hitPattern48 |
| Hit pattern of 48 wires. | |
| std::vector< const TRGSignalVector * > | _priTiming16 |
| Timing of the priority cells (2ns LSB) VHDL : type PriTiming is array (2 downto 0) of std_logic;. | |
| std::vector< const TRGSignalVector * > | _fasTiming16 |
| Timing of the fastest hit in PTS (2ns LSB) VHDL : type FasTiming is array (2 downto 0) of std_logic;. | |
| TRGSignalVector | _clkCounter |
| Clock counter VHDL : type ClkCounter is array (31 downto 0) of std_logic;. | |
| const std::string | _name |
| Name of a link. | |
| const TRGClock * | _clock |
| Used clock. | |
| std::vector< const TRGSignal * > | _head |
| Signal header. | |
| std::vector< const TRGSignal * > | _trail |
| Signal trailer. | |
| std::vector< const TRGSignal * > | _data |
| Signal storage. | |
A class to represent a serial link between trigger modules.
Definition at line 33 of file OpticalLinkFrontEnd.h.
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inherited |
dumps contents.
"message" is to select information to dump. "pre" will be printed in head of each line.
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private |