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Neuro Struct Reference
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unpacker for the Neuro More...

Inheritance diagram for Neuro:
SubTrigger

Public Member Functions

 Neuro (StoreArray< NNBitStream > *arrPtr, const std::string &inName, unsigned inEventWidth, unsigned inOffset, unsigned inHeaderSize, const std::vector< int > &inNodeID, const std::vector< int > &inNodeID_pcie40, int &inDelay, int &inCnttrg, int inDebugLevel)
 Constructor.
 
void reserve (int subDetectorId, std::array< int, nFinesse > nWords, bool pciedata) override
 Calculate the number of clocks in the data, reserve that much of clocks in the Bitstream(s)
 
void unpack (int subDetectorId, std::array< int *, nFinesse > data32tab, std::array< int, nFinesse > nWords, bool pciedata) override
 Unpack the Belle2Link data and fill the Bitstream.
 
virtual int getHeaders (int subDetectorId, std::array< int *, 48 > data32tab, std::array< int, 48 > nWords, bool pciedata)
 Get the Belle2Link header information.
 

Public Attributes

StoreArray< NNBitStream > * ArrayPtr
 Array pointer for NN.
 
unsigned iTracker
 Tracker board ID.
 
unsigned offsetBitWidth
 Offset bit width.
 
std::string name
 Name of the UT3.
 
unsigned eventWidth
 Size of an event in the Belle2Link data in 32-bit words.
 
unsigned offset
 The starting point of the data in an event.
 
int headerSize
 Size of the B2L header in words.
 
int iNode
 COPPER id of the board.
 
int iFinesse
 FINESSE (HSLB) id) of the board.
 
int iNode_pcie40
 PCIe40 id of the board.
 
int iFinesse_pcie40
 PCIe40 ch id of the board.
 
std::string firmwareType
 type of the FPGA firmware
 
std::string firmwareVersion
 version of the FPGA firmware
 
int & delay
 Reference to the variable of its Belle2Link delay.
 
int & cnttrg
 counter of trgger signal, total 32 bits, the 20 LSBs recorded in the event header
 
int debugLevel
 debug level in the steering file
 

Detailed Description

unpacker for the Neuro

Definition at line 449 of file CDCTriggerUnpackerModule.cc.

Constructor & Destructor Documentation

◆ Neuro()

Neuro ( StoreArray< NNBitStream > *  arrPtr,
const std::string &  inName,
unsigned  inEventWidth,
unsigned  inOffset,
unsigned  inHeaderSize,
const std::vector< int > &  inNodeID,
const std::vector< int > &  inNodeID_pcie40,
int &  inDelay,
int &  inCnttrg,
int  inDebugLevel 
)
inline

Constructor.

Definition at line 451 of file CDCTriggerUnpackerModule.cc.

455 :
456 SubTrigger(inName, inEventWidth, inOffset / wordWidth, inHeaderSize, inNodeID, inNodeID_pcie40,
457 inDelay, inCnttrg, inDebugLevel),
458 ArrayPtr(arrPtr),
459 iTracker(std::stoul(inName.substr(inName.length() - 1))),
460 offsetBitWidth(inOffset) {};
Belle2::wordWidth
static constexpr int wordWidth
width of a single word in the raw int buffer
Definition: CDCTriggerUnpackerModule.h:49
Belle2::Neuro::ArrayPtr
StoreArray< NNBitStream > * ArrayPtr
Array pointer for NN.
Definition: CDCTriggerUnpackerModule.cc:463
Belle2::Neuro::offsetBitWidth
unsigned offsetBitWidth
Offset bit width.
Definition: CDCTriggerUnpackerModule.cc:467
Belle2::Neuro::iTracker
unsigned iTracker
Tracker board ID.
Definition: CDCTriggerUnpackerModule.cc:465
Belle2::SubTrigger
enum class SubTriggerType : unsigned char {Merger, TSF, T2D, T3D, Neuro, ETF};
Definition: CDCTriggerUnpackerModule.h:58

Member Function Documentation

◆ getHeaders()

virtual int getHeaders ( int  subDetectorId,
std::array< int *, 48 >  data32tab,
std::array< int, 48 >  nWords,
bool  pciedata 
)
inlinevirtualinherited

Get the Belle2Link header information.

Parameters
subDetectorIdCOPPER id of the current data
data32tablist of pointers to the Belle2Link data buffers
nWordsNumber of words of each FINESSE in the COPPER
pciedataSwitch between PCIe 40 and COPPER
Returns
1 if there are data other than the header

Definition at line 128 of file CDCTriggerUnpackerModule.h.

132 {
133
134 int iNode_i = 0;
135 int iFinesse_i = 0;
136 if (pciedata) {
137 iNode_i = iNode_pcie40;
138 iFinesse_i = iFinesse_pcie40;
139 } else {
140 iNode_i = iNode;
141 iFinesse_i = iFinesse;
142 }
143
144 if (subDetectorId != iNode_i) {
145 return 0;
146 }
147 // int nWordsize = 3075; // temporary solution to hard coded the correct event size (for 2D only?)
148 // empty data buffer
149 if (nWords[iFinesse_i] < headerSize) {
150 B2WARNING("The module " << name << " does not have enough data (" <<
151 nWords[iFinesse_i] << "). Nothing will be unpacked.");
152 return 0;
153 } else if (nWords[iFinesse_i] == headerSize) {
154 B2DEBUG(20, "The module " << name <<
155 " contains only the header. Nothing will be unpacked.");
156 return 0;
157 }
158
159 // need one more check, give a warning if the event has wrong data size
160
161 // event data block header:
162 // 0xdddd --> correct event data (for 2D only?)
163 // 0xbbbb --> dummy buffer supposed to be used for only suppressed events.
164 if (nWords[iFinesse_i] > headerSize) {
165 //dataHeader = CDCTriggerUnpacker::rawIntToAscii(data32tab.at(iFinesse)[headerSize]&0xFFFF0000 >> 16);
166 //bool dataHeader = ( (data32tab.at(iFinesse)[headerSize]&0xffff0000) == 0xdddd0000);
167 long dataHeader = (data32tab.at(iFinesse_i)[headerSize] & 0xffff0000);
168 if (dataHeader != 0xdddd0000) {
169 B2DEBUG(30, "The module " << name << " has an event data header " << std::hex << std::setfill('0') << std::setw(4) <<
170 (dataHeader >> 16) <<
171 " in this event. It will be ignore.");
172 return 0;
173 }
174 B2DEBUG(50, "subdet and head size " << std::setfill('0') << std::hex << std::setw(8) << iNode_i << ", " << std::dec << std::setw(
175 0) << nWords[iFinesse_i] <<
176 " : " << std::hex << std::setw(8) << data32tab.at(iFinesse_i)[0] << " " << data32tab.at(iFinesse_i)[1] << " " << data32tab.at(
177 iFinesse_i)[2] <<
178 " " << data32tab.at(iFinesse_i)[3] << " dataheader = " << dataHeader);
179 }
180
181 /* get event header information
182 * Ideally, these parameters should not change in the same run,
183 * so it is more efficiency to do it in beginRun().
184 * However, since they are present in all events,
185 * let's check if they really remain unchanged.
186 */
187 if (headerSize >= 2) {
188 // supposedly these two Words will stay for all the versions
189 firmwareType = CDCTriggerUnpacker::rawIntToAscii(data32tab.at(iFinesse_i)[0]);
190 firmwareVersion = CDCTriggerUnpacker::rawIntToString(data32tab.at(iFinesse_i)[1]);
191 //int cnttrg = 0; // temporary solution, this should be one as a reference for comparison
192 int l1_revoclk = -1;
193
194 if (headerSize >= 3) {
195 std::bitset<wordWidth> thirdWord(data32tab.at(iFinesse_i)[2]);
196 l1_revoclk = CDCTriggerUnpacker::subset<32, 0, 11>(thirdWord).to_ulong();
197
198 if (firmwareType == "2D ") { // temporary solcuion, the following version number check is valid only for 2D
199
200 if (firmwareVersion > "19041700") { // started since 19041705
201 // the third word is cnttrg and L1_revoclk
202 int newCnttrg = CDCTriggerUnpacker::subset<32, 12, 31>(thirdWord).to_ulong();
203 cnttrg = newCnttrg;
204 } else if (firmwareVersion > "17121900") { // upto that version, headerSize == 2?
205 // the third word is b2l delay and L1_revoclk
206 int newDelay = CDCTriggerUnpacker::subset<32, 12, 20>
207 (thirdWord).to_ulong(); // or should be <32,12,19>? bit 31-20 are for prescale?
208 if (delay > 0 && delay != newDelay) {
209 B2WARNING(" the Belle2Link delay for " << name <<
210 "has changed from " << delay << " to " << newDelay << "!");
211 }
212 delay = newDelay;
213 }
214 }
215 }
216
217 B2DEBUG(20, name << ": " << firmwareType << ", version " <<
218 firmwareVersion << ", node " << std::hex << iNode_i <<
219 ", finesse " << iFinesse_i << ", delay: " << delay <<
220 ", cnttrg: " << cnttrg << std::dec << " == " << cnttrg << ", L1_revoclk " << l1_revoclk);
221
222
223 }
224 return 1;
225 };
Belle2::SubTrigger::iNode_pcie40
int iNode_pcie40
PCIe40 id of the board.
Definition: CDCTriggerUnpackerModule.h:84
Belle2::SubTrigger::headerSize
int headerSize
Size of the B2L header in words.
Definition: CDCTriggerUnpackerModule.h:78
Belle2::SubTrigger::firmwareVersion
std::string firmwareVersion
version of the FPGA firmware
Definition: CDCTriggerUnpackerModule.h:92
Belle2::SubTrigger::firmwareType
std::string firmwareType
type of the FPGA firmware
Definition: CDCTriggerUnpackerModule.h:90
Belle2::SubTrigger::iFinesse
int iFinesse
FINESSE (HSLB) id) of the board.
Definition: CDCTriggerUnpackerModule.h:82
Belle2::SubTrigger::delay
int & delay
Reference to the variable of its Belle2Link delay.
Definition: CDCTriggerUnpackerModule.h:94
Belle2::SubTrigger::iFinesse_pcie40
int iFinesse_pcie40
PCIe40 ch id of the board.
Definition: CDCTriggerUnpackerModule.h:86
Belle2::SubTrigger::cnttrg
int & cnttrg
counter of trgger signal, total 32 bits, the 20 LSBs recorded in the event header
Definition: CDCTriggerUnpackerModule.h:96
Belle2::SubTrigger::name
std::string name
Name of the UT3.
Definition: CDCTriggerUnpackerModule.h:72
Belle2::SubTrigger::iNode
int iNode
COPPER id of the board.
Definition: CDCTriggerUnpackerModule.h:80

◆ reserve()

void reserve ( int  ,
std::array< int, nFinesse >  ,
bool   
)
inlineoverridevirtual

Calculate the number of clocks in the data, reserve that much of clocks in the Bitstream(s)

Reimplemented from SubTrigger.

Definition at line 469 of file CDCTriggerUnpackerModule.cc.

470 {
471 int iNode_i = 0;
472 int iFinesse_i = 0;
473 if (pciedata) {
474 iNode_i = iNode_pcie40;
475 iFinesse_i = iFinesse_pcie40;
476 } else {
477 iNode_i = iNode;
478 iFinesse_i = iFinesse;
479 }
480
481 size_t nClocks = (nWords[iFinesse_i] - headerSize) / eventWidth;
482 size_t entries = ArrayPtr->getEntries();
483 if (subDetectorId == iNode_i) {
484 if (entries == 0) {
485 for (unsigned i = 0; i < nClocks; ++i) {
486 NNBitStream* nnclock = ArrayPtr->appendNew();
487 // fill bitstreams for all trackers with zeros
488 for (unsigned j = 0; j < nTrackers; ++j) {
489 nnclock->m_signal[j].fill(zero_val);
490 }
491 }
492 B2DEBUG(20, name << ": " << nClocks << " clocks");
493 } else if (entries != nClocks) {
494 B2DEBUG(20, "Number of clocks in " << name << " conflicts with others!");
495 }
496 }
497 };
Belle2::Bitstream
Class to hold one clock cycle of raw bit content.
Definition: Bitstream.h:54
Belle2::Bitstream::m_signal
SignalBus m_signal
SignalBus of the Bitstream.
Definition: Bitstream.h:77
Belle2::StoreArray::appendNew
T * appendNew()
Construct a new T object at the end of the array.
Definition: StoreArray.h:246
Belle2::StoreArray::getEntries
int getEntries() const
Get the number of objects in the array.
Definition: StoreArray.h:216
Belle2::SubTrigger::eventWidth
unsigned eventWidth
Size of an event in the Belle2Link data in 32-bit words.
Definition: CDCTriggerUnpackerModule.h:74

◆ unpack()

void unpack ( int  ,
std::array< int *, nFinesse >  ,
std::array< int, nFinesse >  ,
bool   
)
inlineoverridevirtual

Unpack the Belle2Link data and fill the Bitstream.

Reimplemented from SubTrigger.

Definition at line 499 of file CDCTriggerUnpackerModule.cc.

503 {
504 int iNode_i = 0;
505 int iFinesse_i = 0;
506 if (pciedata) {
507 iNode_i = iNode_pcie40;
508 iFinesse_i = iFinesse_pcie40;
509 } else {
510 iNode_i = iNode;
511 iFinesse_i = iFinesse;
512 }
513
514 if (subDetectorId != iNode_i) {
515 return;
516 }
517 // make bitstream
518 // loop over all clocks
519 for (int i = headerSize; i < nWords[iFinesse_i]; i += eventWidth) {
520 int iclock = (i - headerSize) / eventWidth;
521 auto nnclock = (*ArrayPtr)[iclock];
522 B2DEBUG(20, "clock " << iclock);
523 if (debugLevel >= 300) {
524 printBuffer(data32tab[iFinesse_i] + headerSize + eventWidth * iclock,
525 eventWidth);
526 }
527 // fill output
528 for (unsigned pos = 0; pos < NN_WIDTH; ++pos) {
529 const int j = (offsetBitWidth + pos) / wordWidth;
530 const int k = (offsetBitWidth + pos) % wordWidth;
531 std::bitset<wordWidth> word(data32tab[iFinesse_i][i + j]);
532 nnclock->m_signal[iTracker][pos] = std_logic(word[wordWidth - 1 - k]);
533 }
534 if (debugLevel >= 100) {
535 display_hex(nnclock->m_signal[iTracker]);
536 }
537 }
538 }
Cosim::display_hex
void display_hex(const std::array< char, N > &signal)
Display signal in hex.
Definition: Cosim.h:81
Belle2::SubTrigger::debugLevel
int debugLevel
debug level in the steering file
Definition: CDCTriggerUnpackerModule.h:99

Member Data Documentation

◆ ArrayPtr

StoreArray<NNBitStream>* ArrayPtr

Array pointer for NN.

Definition at line 463 of file CDCTriggerUnpackerModule.cc.

◆ cnttrg

int& cnttrg
inherited

counter of trgger signal, total 32 bits, the 20 LSBs recorded in the event header

Definition at line 96 of file CDCTriggerUnpackerModule.h.

◆ debugLevel

int debugLevel
inherited

debug level in the steering file

Definition at line 99 of file CDCTriggerUnpackerModule.h.

◆ delay

int& delay
inherited

Reference to the variable of its Belle2Link delay.

Definition at line 94 of file CDCTriggerUnpackerModule.h.

◆ eventWidth

unsigned eventWidth
inherited

Size of an event in the Belle2Link data in 32-bit words.

Definition at line 74 of file CDCTriggerUnpackerModule.h.

◆ firmwareType

std::string firmwareType
inherited

type of the FPGA firmware

Definition at line 90 of file CDCTriggerUnpackerModule.h.

◆ firmwareVersion

std::string firmwareVersion
inherited

version of the FPGA firmware

Definition at line 92 of file CDCTriggerUnpackerModule.h.

◆ headerSize

int headerSize
inherited

Size of the B2L header in words.

Definition at line 78 of file CDCTriggerUnpackerModule.h.

◆ iFinesse

int iFinesse
inherited

FINESSE (HSLB) id) of the board.

Definition at line 82 of file CDCTriggerUnpackerModule.h.

◆ iFinesse_pcie40

int iFinesse_pcie40
inherited

PCIe40 ch id of the board.

Definition at line 86 of file CDCTriggerUnpackerModule.h.

◆ iNode

int iNode
inherited

COPPER id of the board.

Definition at line 80 of file CDCTriggerUnpackerModule.h.

◆ iNode_pcie40

int iNode_pcie40
inherited

PCIe40 id of the board.

Definition at line 84 of file CDCTriggerUnpackerModule.h.

◆ iTracker

unsigned iTracker

Tracker board ID.

Definition at line 465 of file CDCTriggerUnpackerModule.cc.

◆ name

std::string name
inherited

Name of the UT3.

Definition at line 72 of file CDCTriggerUnpackerModule.h.

◆ offset

unsigned offset
inherited

The starting point of the data in an event.

Definition at line 76 of file CDCTriggerUnpackerModule.h.

◆ offsetBitWidth

unsigned offsetBitWidth

Offset bit width.

Definition at line 467 of file CDCTriggerUnpackerModule.cc.

The documentation for this struct was generated from the following file: