Belle II Software  release-08-01-10
trggdlSummaryModule.cc
1 /**************************************************************************
2  * basf2 (Belle II Analysis Software Framework) *
3  * Author: The Belle II Collaboration *
4  * *
5  * See git log for contributors and copyright holders. *
6  * This file is licensed under LGPL-3.0, see LICENSE.md. *
7  **************************************************************************/
8 //---------------------------------------------------------------
9 // $Id$
10 //---------------------------------------------------------------
11 // Filename : trggdlSummaryModule.cc
12 // Section : TRG GDL Summary
13 // Owner :
14 // Email :
15 //---------------------------------------------------------------
16 // Description : A trigger module for TRG GDL
17 //---------------------------------------------------------------
18 // 1.00 : 2017/05/08 : First version
19 //---------------------------------------------------------------
20 #include <trg/gdl/modules/trggdlSummary/trggdlSummaryModule.h>
21 
22 #include <framework/datastore/StoreArray.h>
23 
24 #include <mdst/dataobjects/TRGSummary.h>
25 
26 #include <framework/database/DBObjPtr.h>
27 #include <mdst/dbobjects/TRGGDLDBInputBits.h>
28 #include <mdst/dbobjects/TRGGDLDBFTDLBits.h>
29 
30 #include <string.h>
31 
32 
33 using namespace Belle2;
34 using namespace GDL;
35 
36 REG_MODULE(TRGGDLSummary);
37 
39  : Module::Module()
40 {
41 
42  setDescription("Fill experiment data to TRGSummary");
44  addParam("debugLevel", _debugLevel, "Debug Level", 0);
45 
46 }
47 
49 {
50 
51  if (_debugLevel > 9) printf("TRGGDLSummaryModule::initialize() start\n");
52 
53  GDLResult.registerInDataStore();
54  for (int i = 0; i < 320; i++) {
55  LeafBitMap[i] = m_unpacker->getLeafMap(i);
56  }
57  for (int i = 0; i < 320; i++) {
58  strcpy(LeafNames[i], m_unpacker->getLeafnames(i));
59  }
60 
61  _e_timtype = 0;
62  _e_rvcout = 0;
63  for (int i = 0; i < 10; i++) {
64  ee_psn[i] = 0;
65  ee_ftd[i] = 0;
66  ee_itd[i] = 0;
67  }
68  for (int i = 0; i < 320; i++) {
69  if (strcmp(LeafNames[i], "timtype") == 0)_e_timtype = LeafBitMap[i];
70  if (strcmp(LeafNames[i], "rvcout") == 0) _e_rvcout = LeafBitMap[i];
71  if (strcmp(LeafNames[i], "psn0") == 0) ee_psn[0] = LeafBitMap[i];
72  if (strcmp(LeafNames[i], "psn1") == 0) ee_psn[1] = LeafBitMap[i];
73  if (strcmp(LeafNames[i], "psn2") == 0) ee_psn[2] = LeafBitMap[i];
74  if (strcmp(LeafNames[i], "psn3") == 0) ee_psn[3] = LeafBitMap[i];
75  if (strcmp(LeafNames[i], "psn4") == 0) ee_psn[4] = LeafBitMap[i];
76  if (strcmp(LeafNames[i], "psn5") == 0) ee_psn[5] = LeafBitMap[i];
77  if (strcmp(LeafNames[i], "psn6") == 0) ee_psn[6] = LeafBitMap[i];
78  if (strcmp(LeafNames[i], "psn7") == 0) ee_psn[7] = LeafBitMap[i];
79  if (strcmp(LeafNames[i], "psn8") == 0) ee_psn[8] = LeafBitMap[i];
80  if (strcmp(LeafNames[i], "psn9") == 0) ee_psn[9] = LeafBitMap[i];
81  if (strcmp(LeafNames[i], "ftd0") == 0) ee_ftd[0] = LeafBitMap[i];
82  if (strcmp(LeafNames[i], "ftd1") == 0) ee_ftd[1] = LeafBitMap[i];
83  if (strcmp(LeafNames[i], "ftd2") == 0) ee_ftd[2] = LeafBitMap[i];
84  if (strcmp(LeafNames[i], "ftd3") == 0) ee_ftd[3] = LeafBitMap[i];
85  if (strcmp(LeafNames[i], "ftd4") == 0) ee_ftd[4] = LeafBitMap[i];
86  if (strcmp(LeafNames[i], "ftd5") == 0) ee_ftd[5] = LeafBitMap[i];
87  if (strcmp(LeafNames[i], "ftd6") == 0) ee_ftd[6] = LeafBitMap[i];
88  if (strcmp(LeafNames[i], "ftd7") == 0) ee_ftd[7] = LeafBitMap[i];
89  if (strcmp(LeafNames[i], "ftd8") == 0) ee_ftd[8] = LeafBitMap[i];
90  if (strcmp(LeafNames[i], "ftd9") == 0) ee_ftd[9] = LeafBitMap[i];
91  if (strcmp(LeafNames[i], "itd0") == 0) ee_itd[0] = LeafBitMap[i];
92  if (strcmp(LeafNames[i], "itd1") == 0) ee_itd[1] = LeafBitMap[i];
93  if (strcmp(LeafNames[i], "itd2") == 0) ee_itd[2] = LeafBitMap[i];
94  if (strcmp(LeafNames[i], "itd3") == 0) ee_itd[3] = LeafBitMap[i];
95  if (strcmp(LeafNames[i], "itd4") == 0) ee_itd[4] = LeafBitMap[i];
96  if (strcmp(LeafNames[i], "itd5") == 0) ee_itd[5] = LeafBitMap[i];
97  if (strcmp(LeafNames[i], "itd6") == 0) ee_itd[6] = LeafBitMap[i];
98  if (strcmp(LeafNames[i], "itd7") == 0) ee_itd[7] = LeafBitMap[i];
99  if (strcmp(LeafNames[i], "itd8") == 0) ee_itd[8] = LeafBitMap[i];
100  if (strcmp(LeafNames[i], "itd9") == 0) ee_itd[9] = LeafBitMap[i];
101  }
102 
103 
104  if (_debugLevel > 9) printf("TRGGDLSummaryModule::initialize() end\n");
105 }
106 
108 {
109 
110  if (_debugLevel > 9) printf("TRGGDLSummaryModule::event() start\n");
111 
112  int n_leafs = 0;
113  n_leafs = m_unpacker->getnLeafs();
114  int n_leafsExtra = 0;
115  n_leafsExtra = m_unpacker->getnLeafsExtra();
116  int n_clocks = m_unpacker->getnClks();
117  int nconf = m_unpacker->getconf();
118  int nword_input = m_unpacker->get_nword_input();
119  int nword_output = m_unpacker->get_nword_output();
120 
121  if (_debugLevel > 89)
122  printf("trggdlSummaryModule:n_leafs(%d), n_leafsExtra(%d), n_clocks(%d), nconf(%d), nword_input(%d), nword_output(%d)\n",
123  n_leafs, n_leafsExtra, n_clocks, nconf, nword_input, nword_output);
124 
126  if (!entAry || !entAry.getEntries()) return;
127 
128  //prepare entAry adress
129  int clk_map = 0;
130  for (int i = 0; i < 320; i++) {
131  if (strcmp(entAry[0]->m_unpackername[i], "clk") == 0) clk_map = i;
132  }
133  if (_debugLevel > 89)
134  printf("trggdlSummaryModule:clk_map(%d)\n", clk_map);
135 
136  std::vector<std::vector<int> > _data(n_leafs + n_leafsExtra);
137  for (int leaf = 0; leaf < n_leafs + n_leafsExtra; leaf++) {
138  std::vector<int> _v(n_clocks);
139  _data[leaf] = _v;
140  }
141 
142  // fill "bit vs clk" for the event
143  for (int ii = 0; ii < entAry.getEntries(); ii++) {
144  if (_debugLevel > 89)
145  printf("trggdlSummaryModule:a:ii(%d)\n", ii);
146  std::vector<int*> Bits(n_leafs + n_leafsExtra);
147  //set pointer
148  for (int i = 0; i < 320; i++) {
149  if (LeafBitMap[i] != -1) {
150  Bits[LeafBitMap[i]] = &(entAry[ii]->m_unpacker[i]);
151  if (_debugLevel > 89)
152  printf("trggdlSummaryModule:ab:i(%d), LeafBitMap[i](%d), *Bits[LeafBitMap[i]](%d)\n",
153  i, LeafBitMap[i], *Bits[LeafBitMap[i]]);
154  } else {
155  if (_debugLevel > 89)
156  printf("trggdlSummaryModule:ab:i(%d), LeafBitMap[i](%d)\n",
157  i, LeafBitMap[i]);
158  }
159  }
160  for (int leaf = 0; leaf < n_leafs + n_leafsExtra; leaf++) {
161  if (_debugLevel > 89)
162  printf("trggdlSummaryModule:ad:leaf(%d),ii(%d),clk_map(%d),*Bits[leaf](%d), entAry[ii]->m_unpacker[clk_map](%d)\n",
163  leaf, ii, clk_map, *Bits[leaf], entAry[ii]->m_unpacker[clk_map]);
164  _data[leaf][entAry[ii]->m_unpacker[clk_map]] = *Bits[leaf];
165  }
166  }
167 
168  GDLResult.create(true);
169 
170  unsigned ored = 0;
171 
172  for (int j = 0; j < (int)nword_input; j++) {
173  if (_debugLevel > 89) printf("b:j(%d),", j);
174  ored = 0;
175  for (int clk = 0; clk < n_clocks; clk++) {
176  if (_debugLevel > 89) printf("clk(%d),", clk);
177  ored |= _data[ee_itd[j]][clk];
178  }
179  GDLResult->setInputBits(j, ored);
180  if (_debugLevel > 89) printf("\n");
181  }
182 
183  if (nconf == 0) {
184  ored = 0;
185  for (int clk = 0; clk < n_clocks; clk++) {
186  ored |= _data[ee_ftd[0]][clk];
187  }
188  GDLResult->setFtdlBits(0, ored);
189 
190  ored = 0;
191  for (int clk = 0; clk < n_clocks; clk++) {
192  ored |= (_data[ee_ftd[2]][clk] << 16) + _data[ee_ftd[1]][clk];
193  }
194  GDLResult->setFtdlBits(1, ored);
195 
196  ored = 0;
197  for (int clk = 0; clk < n_clocks; clk++) {
198  ored |= _data[ee_psn[0]][clk];
199  }
200  GDLResult->setPsnmBits(0, ored);
201 
202  ored = 0;
203  for (int clk = 0; clk < n_clocks; clk++) {
204  ored |= (_data[ee_psn[2]][clk] << 16) + _data[ee_psn[1]][clk];
205  }
206  GDLResult->setPsnmBits(1, ored);
207  } else {
208  for (int j = 0; j < (int)nword_output; j++) {
209  ored = 0;
210  for (int clk = 0; clk < n_clocks; clk++) {
211  ored |= _data[ee_ftd[j]][clk];
212  }
213  GDLResult->setFtdlBits(j, ored);
214  }
215 
216  for (int j = 0; j < (int)nword_output; j++) {
217  ored = 0;
218  for (int clk = 0; clk < n_clocks; clk++) {
219  ored |= _data[ee_psn[j]][clk];
220  }
221  GDLResult->setPsnmBits(j, ored);
222  }
223  }
224 
225  // reg_tmdl_timtype in header. 3bit, no quality info.
226  GDL::EGDLTimingType gtt = (GDL::EGDLTimingType)_data[_e_timtype][0];
227 
228  //get prescales
229  for (int i = 0; i < 320; i++) {
230  int bit1 = i / 32;
231  int bit2 = i % 32;
232  GDLResult->setPreScale(bit1, bit2, m_prescales->getprescales(i));
233  }
234 
236  if (gtt == GDL::e_tt_cdc) {
238  } else if (gtt == GDL::e_tt_ecl) {
240  } else if (gtt == GDL::e_tt_top) {
242  } else if (gtt == GDL::e_tt_dphy) {
244  } else if (gtt == GDL::e_tt_rand) {
246  } else if (gtt == GDL::e_tt_psnm) {
248  } else {
250  }
251 
253  unsigned _exp = bevt->getExperiment();
254  unsigned _run = bevt->getRun();
255  unsigned exprun = _exp * 1000000 + _run;
256  if (exprun < 13000500) {
257  GDLResult->setTimQuality(TRGSummary::TTYQ_CORS); // coarse
258  } else {
259  int rvcout = _data[_e_rvcout][0];
260  int q = (rvcout >> 1) & 3;
261  TRGSummary::ETimingQuality timQuality = TRGSummary::TTYQ_NONE;
262  switch (q) {
263  case 1:
264  timQuality = TRGSummary::TTYQ_CORS;
265  break;
266  case 2:
267  timQuality = TRGSummary::TTYQ_FINE;
268  break;
269  case 3:
270  timQuality = TRGSummary::TTYQ_SFIN;
271  break;
272  default:
273  timQuality = TRGSummary::TTYQ_NONE;
274  break;
275  }
276  GDLResult->setTimQuality(timQuality);
277  }
278 
279  if (exprun > 16000271) {
280  if (tt == TRGSummary::TTYP_RAND) {
281  int i_poissonin = GDLResult->getInputBitNumber(std::string("poissonin"));
282  int j_poissonin = i_poissonin / TRGSummary::c_trgWordSize;
283  int k_poissonin = i_poissonin % TRGSummary::c_trgWordSize;
284  int i_veto = GDLResult->getInputBitNumber(std::string("veto"));
285  int j_veto = i_veto / TRGSummary::c_trgWordSize;
286  int k_veto = i_veto % TRGSummary::c_trgWordSize;
287  for (int clk = 5; clk < n_clocks - 5; clk++) {
288  if ((1 << k_poissonin) & _data[ee_itd[j_poissonin]][clk]) {
290  if ((1 << k_veto) & _data[ee_itd[j_veto]][clk]) {
291  GDLResult->setPoissonInInjectionVeto();
292  }
293  }
294  }
295  }
296  }
297  GDLResult->setTimType(tt);
298 
299 }
Base class for Modules.
Definition: Module.h:72
void setDescription(const std::string &description)
Sets the description of the module.
Definition: Module.cc:214
void setPropertyFlags(unsigned int propertyFlags)
Sets the flags for the module properties.
Definition: Module.cc:208
@ c_ParallelProcessingCertified
This module can be run in parallel processing mode safely (All I/O must be done through the data stor...
Definition: Module.h:80
Accessor to arrays stored in the data store.
Definition: StoreArray.h:113
int getEntries() const
Get the number of objects in the array.
Definition: StoreArray.h:216
Type-safe access to single objects in the data store.
Definition: StoreObjPtr.h:96
virtual void initialize() override
initialize
virtual void event() override
Event.
StoreObjPtr< TRGSummary > GDLResult
output for TRGSummary
static const unsigned int c_trgWordSize
size of a l1 trigger word
Definition: TRGSummary.h:37
ETimingType
types of trigger timing source defined in b2tt firmware
Definition: TRGSummary.h:43
@ TTYP_DPHY
delayed physics events for background
Definition: TRGSummary.h:65
@ TTYP_SELF
events triggered by self trigger
Definition: TRGSummary.h:53
@ TTYP_POIS
poisson random trigger
Definition: TRGSummary.h:73
@ TTYP_NONE
reserved (not defined yet)
Definition: TRGSummary.h:75
@ TTYP_TOP
events triggered by TOP timing
Definition: TRGSummary.h:61
@ TTYP_CDC
events triggered by CDC timing
Definition: TRGSummary.h:63
@ TTYP_ECL
events triggered by ECL timing
Definition: TRGSummary.h:45
@ TTYP_RAND
random trigger events
Definition: TRGSummary.h:67
ETimingQuality
trigger timing type quality
Definition: TRGSummary.h:79
REG_MODULE(arichBtest)
Register the Module.
void addParam(const std::string &name, T &paramVariable, const std::string &description, const T &defaultValue)
Adds a new parameter to the module.
Definition: Module.h:560
Abstract base class for different kinds of events.