Tracker2D Struct Reference

unpacker for the 2D tracker More...

Inheritance diagram for Tracker2D:

Public Member Functions
	Tracker2D (StoreArray< TSFOutputBitStream > *inArrayPtr, StoreArray< T2DOutputBitStream > *outArrayPtr, const std::string &inName, unsigned inEventWidth, unsigned inOffset, unsigned inHeaderSize, const std::vector< int > &inNodeID, const std::vector< int > &inNodeID_pcie40, unsigned inNumTS, int &inDelay, int &inCnttrg, int inDebugLevel)
	constructor
void	reserve (int subDetectorId, std::array< int, nFinesse > nWords, bool pciedata) override
	Calculate the number of clocks in the data, reserve that much of clocks in the Bitstream(s)
void	unpack (int subDetectorId, std::array< int *, 48 > data32tab, std::array< int, 48 > nWords, bool pciedata) override
	Unpack the Belle2Link data and fill the Bitstream.
virtual void	unpack (int, std::array< int *, nFinesse >, std::array< int, nFinesse >, bool)
	Unpack the Belle2Link data and fill the Bitstream.
virtual int	getHeaders (int subDetectorId, std::array< int *, 48 > data32tab, std::array< int, 48 > nWords, bool pciedata)
	Get the Belle2Link header information.

Public Attributes
StoreArray< TSFOutputBitStream > *	inputArrayPtr
	pointer to the Bitstream of 2D input
StoreArray< T2DOutputBitStream > *	outputArrayPtr
	pointer to the Bitstream of 2D output to 3D/Neuro
unsigned	iTracker
	ID of the 2D tracker (0 to 3)
unsigned	numTS
	Number of TS sent to 2D (0 to 20)
unsigned	offsetBitWidth
	starting point of the input data in an Belle2Link event
std::string	name
	Name of the UT3.
unsigned	eventWidth
	Size of an event in the Belle2Link data in 32-bit words.
unsigned	offset
	The starting point of the data in an event.
int	headerSize
	Size of the B2L header in words.
int	iNode
	COPPER id of the board.
int	iFinesse
	FINESSE (HSLB) id) of the board.
int	iNode_pcie40
	PCIe40 id of the board.
int	iFinesse_pcie40
	PCIe40 ch id of the board.
std::string	firmwareType
	type of the FPGA firmware
std::string	firmwareVersion
	version of the FPGA firmware
int &	delay
	Reference to the variable of its Belle2Link delay.
int &	cnttrg
	counter of trgger signal, total 32 bits, the 20 LSBs recorded in the event header
int	debugLevel
	debug level in the steering file

Detailed Description

unpacker for the 2D tracker

Definition at line 155 of file CDCTriggerUnpackerModule.cc.

Constructor & Destructor Documentation

Tracker2D()

Tracker2D ( StoreArray< TSFOutputBitStream > *  inArrayPtr, StoreArray< T2DOutputBitStream > *  outArrayPtr, const std::string &  inName, unsigned  inEventWidth, unsigned  inOffset, unsigned  inHeaderSize, const std::vector< int > &  inNodeID, const std::vector< int > &  inNodeID_pcie40, unsigned  inNumTS, int &  inDelay, int &  inCnttrg, int  inDebugLevel  )

inline

constructor

Definition at line 157 of file CDCTriggerUnpackerModule.cc.

                                :
      SubTrigger(inName, inEventWidth, inOffset / wordWidth, inHeaderSize, inNodeID, inNodeID_pcie40,
                 inDelay, inCnttrg, inDebugLevel),
      inputArrayPtr(inArrayPtr), outputArrayPtr(outArrayPtr),
      iTracker(std::stoul(inName.substr(inName.length() - 1))),
      numTS(inNumTS), offsetBitWidth(inOffset) {};

Member Function Documentation

getHeaders()

virtual int getHeaders ( int  subDetectorId, std::array< int *, 48 >  data32tab, std::array< int, 48 >  nWords, bool  pciedata  )

inlinevirtualinherited

Get the Belle2Link header information.

Parameters

subDetectorId	COPPER id of the current data
data32tab	list of pointers to the Belle2Link data buffers
nWords	Number of words of each FINESSE in the COPPER
pciedata	Switch between PCIe 40 and COPPER

Returns

1 if there are data other than the header

Definition at line 128 of file CDCTriggerUnpackerModule.h.

    {
 
      int iNode_i = 0;
      int iFinesse_i = 0;
      if (pciedata) {
        iNode_i = iNode_pcie40;
        iFinesse_i = iFinesse_pcie40;
      } else {
        iNode_i = iNode;
        iFinesse_i = iFinesse;
      }
 
      if (subDetectorId != iNode_i) {
        return 0;
      }
      // int nWordsize = 3075;  // temporary solution to hard coded the correct event size (for 2D only?)
      // empty data buffer
      if (nWords[iFinesse_i] < headerSize) {
        B2WARNING("The module " << name << " does not have enough data (" <<
                  nWords[iFinesse_i] << "). Nothing will be unpacked.");
        return 0;
      } else if (nWords[iFinesse_i] == headerSize) {
        B2DEBUG(20, "The module " << name <<
                " contains only the header. Nothing will be unpacked.");
        return 0;
      }
 
      // need one more check, give a warning if the event has wrong data size
 
      // event data block header:
      // 0xdddd  --> correct event data (for 2D only?)
      // 0xbbbb  --> dummy buffer supposed to be used for only suppressed events.
      if (nWords[iFinesse_i] > headerSize) {
        //dataHeader = CDCTriggerUnpacker::rawIntToAscii(data32tab.at(iFinesse)[headerSize]&0xFFFF0000 >> 16);
        //bool dataHeader = ( (data32tab.at(iFinesse)[headerSize]&0xffff0000) == 0xdddd0000);
        long dataHeader = (data32tab.at(iFinesse_i)[headerSize] & 0xffff0000);
        if (dataHeader != 0xdddd0000) {
          B2DEBUG(30, "The module " << name << " has an event data header " << std::hex << std::setfill('0') << std::setw(4) <<
                  (dataHeader >> 16) <<
                  " in this event. It will be ignore.");
          return 0;
        }
        B2DEBUG(50, "subdet and head size " <<  std::setfill('0') << std::hex << std::setw(8) << iNode_i << ", " << std::dec <<  std::setw(
                  0) << nWords[iFinesse_i] <<
                " : " << std::hex << std::setw(8) << data32tab.at(iFinesse_i)[0] << " " << data32tab.at(iFinesse_i)[1] << " " << data32tab.at(
                  iFinesse_i)[2] <<
                " " << data32tab.at(iFinesse_i)[3] << " dataheader = " << dataHeader);
      }
 
      /* get event header information
       * Ideally, these parameters should not change in the same run,
       * so it is more efficiency to do it in beginRun().
       * However, since they are present in all events,
       * let's check if they really remain unchanged.
       */
      if (headerSize >= 2) {
        // supposedly these two Words will stay for all the versions
        firmwareType = CDCTriggerUnpacker::rawIntToAscii(data32tab.at(iFinesse_i)[0]);
        firmwareVersion = CDCTriggerUnpacker::rawIntToString(data32tab.at(iFinesse_i)[1]);
        //int cnttrg = 0;    // temporary solution, this should be one as a reference for comparison
        int l1_revoclk = -1;
 
        if (headerSize >= 3) {
          std::bitset<wordWidth> thirdWord(data32tab.at(iFinesse_i)[2]);
          l1_revoclk = CDCTriggerUnpacker::subset<32, 0, 11>(thirdWord).to_ulong();
 
          if (firmwareType == "2D  ") {  // temporary solcuion, the following version number check is valid only for 2D
 
            if (firmwareVersion >  "19041700")  {  // started since 19041705
              // the third word is cnttrg and L1_revoclk
              int newCnttrg = CDCTriggerUnpacker::subset<32, 12, 31>(thirdWord).to_ulong();
              cnttrg = newCnttrg;
            } else if (firmwareVersion > "17121900") {  // upto that version, headerSize == 2?
              // the third word is b2l delay and L1_revoclk
              int newDelay = CDCTriggerUnpacker::subset<32, 12, 20>
                             (thirdWord).to_ulong();   // or should be <32,12,19>? bit 31-20 are for prescale?
              if (delay > 0 && delay != newDelay) {
                B2WARNING(" the Belle2Link delay for " << name <<
                          "has changed from " << delay << " to " << newDelay << "!");
              }
              delay = newDelay;
            }
          }
        }
 
        B2DEBUG(20, name << ": " << firmwareType << ", version " <<
                firmwareVersion << ", node " << std::hex << iNode_i <<
                ", finesse " << iFinesse_i << ", delay: " << delay <<
                ", cnttrg: " << cnttrg << std::dec << " == " << cnttrg <<  ", L1_revoclk " << l1_revoclk);
 
 
      }
      return 1;
    };

reserve()

void reserve ( int  subDetectorId, std::array< int, nFinesse >  nWords, bool  pciedata  )

inlineoverridevirtual

Calculate the number of clocks in the data, reserve that much of clocks in the Bitstream(s)

Parameters

subDetectorId	COPPER id of the current data
nWords	Number of words of each FINESSE in the COPPER
pciedata	Switch between PCIe 40 and COPPER

Reimplemented from SubTrigger.

Definition at line 189 of file CDCTriggerUnpackerModule.cc.

    {
      int iNode_i = 0;
      int iFinesse_i = 0;
      if (pciedata) {
        iNode_i = iNode_pcie40;
        iFinesse_i = iFinesse_pcie40;
      } else {
        iNode_i = iNode;
        iFinesse_i = iFinesse;
      }
 
      size_t nClocks = (nWords[iFinesse_i] - headerSize) / eventWidth;
      size_t entries = inputArrayPtr->getEntries();
      if (subDetectorId == iNode_i) {
        if (entries == 0) {
          for (unsigned i = 0; i < nClocks; ++i) {
            TSFOutputBitStream* inputClock = inputArrayPtr->appendNew();
            T2DOutputBitStream* outputClock = outputArrayPtr->appendNew();
            // fill bitstreams for all trackers with zeros
            for (unsigned j = 0; j < nTrackers; ++j) {
              for (unsigned iAxialTSF = 0; iAxialTSF < nAxialTSF; ++iAxialTSF) {
                inputClock->m_signal[iAxialTSF][j].fill(zero_val);
              }
              outputClock->m_signal.at(j).fill(zero_val);
            }
          }
          B2DEBUG(20, name << ": " << nClocks << " clocks");
        } else if (entries != nClocks) {
          B2DEBUG(20, "Number of clocks in " << name << " conflicts with others!");
        }
      }
    };

unpack() [1/2]

void unpack ( int  subDetectorId, std::array< int *, 48 >  data32tab, std::array< int, 48 >  nWords, bool  pciedata  )

inlineoverride

Unpack the Belle2Link data and fill the Bitstream.

Parameters

subDetectorId	COPPER id of the current data
data32tab	list of pointers to the Belle2Link data buffers
nWords	Number of words of each FINESSE in the COPPER
pciedata	Switch between PCIe 40 and COPPER

Definition at line 231 of file CDCTriggerUnpackerModule.cc.

    {
      int iNode_i = 0;
      int iFinesse_i = 0;
      if (pciedata) {
        iNode_i = iNode_pcie40;
        iFinesse_i = iFinesse_pcie40;
      } else {
        iNode_i = iNode;
        iFinesse_i = iFinesse;
      }
 
      if (subDetectorId != iNode_i) {
        return;
      }
      // Recently, the content of the last clock appears at the beginning.
      // Now we decide whether we will change the order of the clocks
      // based on the 127MHz counter on the 2nd half of the first word [15:0]
      int ccShift = 0;
      using halfDataWord = std::bitset<16>;
      std::vector<halfDataWord> counters;
      counters.reserve(inputArrayPtr->getEntries());
      for (int iclock = 0; iclock < inputArrayPtr->getEntries(); ++iclock) {
        counters.emplace_back(data32tab[iFinesse_i]
                              [headerSize + eventWidth * iclock] & 0xffff);
        B2DEBUG(100, "iclock " << iclock << " --> " << counters.at(iclock).to_ulong() << " : " << std::hex << counters.at(iclock));
      }
      bool counter_correct_error = false;
      while (counters.at(1).to_ulong() - counters.at(0).to_ulong() != 4) {
        std::rotate(counters.begin(), counters.begin() + 1, counters.end());
        ccShift++;
        // 2019,0410 This situation, looks like clockcounter shifted 6 bits left, was first seen in exp5 data.
        //           Later it has been understood that it is due to data from a dummy BRAM buffer, which is supposed to be used for suppressed data only.
        //           The data header is 0xbbbb instead of 0xdddd.
        //           getHeader in the CDCTriggerUnpackerModule.h is modified to skip this kind event.
        // 2019,0419 unfortunately, clockcounter found disorder since expt 7, run 2553, after update of B2L firmware to replace the b2dly with trigger counter.
        //           for that run, it seems the problem happens only at 2D1, 2D2, and 2D3.
        if (ccShift >= inputArrayPtr->getEntries()) {
          B2DEBUG(90, "PHYSJG: clock counter rotation over one cycle: " << ccShift);
          for (const auto& c : counters) {
            B2DEBUG(90, "" << c.to_ulong() << " : " << std::hex << c);
          }
          counter_correct_error = true;
          break;
        }
      }
      if (counter_correct_error) {
        B2DEBUG(20, "PHYSJG: " <<  name << " too many clock counter rotation corrections: " << ccShift << " data object skipped.");
        // maybe implement an option for user to decide if this data block should be kept or not?!
        return;
      }
      if (! std::is_sorted(counters.begin(), counters.end(),
      [](halfDataWord i, halfDataWord j) {
      return (j.to_ulong() - i.to_ulong() == 4);
      })) {
        B2DEBUG(20, "clock counters are still out of order");
        for (const auto& c : counters) {
          B2DEBUG(90, "" << c.to_ulong());
        }
      }
      // This could happen when the clock counter is over 1279 and roll back to 0, since only 48 clock counter will be in the data.
      if (ccShift) {
        B2DEBUG(15, "shifting the first " << ccShift <<
                " clock(s) to the end for " << name);
      }
 
      // get event body information
      // make bitstream
      // loop over all clocks
      for (int i = headerSize; i < nWords[iFinesse_i]; i += eventWidth) {
        int iclock = (i - headerSize) / eventWidth - ccShift;
        if (iclock < 0) {
          iclock += inputArrayPtr->getEntries();
        }
        auto inputClock = (*inputArrayPtr)[iclock];
        auto outputClock = (*outputArrayPtr)[iclock];
        // clear output bitstream
        outputClock->m_signal.at(iTracker).fill(zero_val);
        B2DEBUG(90, "unpacker clock " << iclock);
        if (debugLevel >= 300) {
          printBuffer(data32tab[iFinesse_i] + headerSize + eventWidth * iclock,
                      eventWidth);
        }
        // get the clock counters
        std::array<dataWord, 2> ccword({
          data32tab[iFinesse_i][i + 2], data32tab[iFinesse_i][i + 3]
        });
        // fill input
        // Careful! this iTSF is (8 - iSL) / 2
        for (unsigned iTSF = 0; iTSF < nAxialTSF; ++iTSF) {
          // clear input bitstream
          inputClock->m_signal[nAxialTSF - 1 - iTSF][iTracker].fill(zero_val);
 
          if (firmwareVersion < "18012600") {
            /*
              data_b2l_r <=
              x"dddd" & cntr125M(15 downto 0) &
              cc(4) & cc(3) & cc(2) & cc(1) & cc(0) &
              ccError &
              -- 82
              tsfs(4)(209 downto 0) &
              tsfs(3)(209 downto 0) &
              tsfs(2)(209 downto 0) &
              tsfs(1)(209 downto 0) &
              tsfs(0)(209 downto 0) &
            */
            // fill the clock counters
            for (unsigned pos = 0; pos < clockCounterWidth; ++pos) {
              const int j = (pos + iTSF * clockCounterWidth) / wordWidth;
              const int k = (pos + iTSF * clockCounterWidth) % wordWidth;
              /* The index behaves differently in each containers
                 Here is an example of a 64-bit wide MSB data
                 |-------- smaller index in the firmware ----->
 
                 data in the firmware/VHDL std_logic_vector(63 downto 0)
                  63 62 61 60 ...                         01 00
 
                 data in B2L/RawTRG (when using std::bitset<32> for a word)
                 (31 30 29 28 ... 01 00) (31 30 29 28 ... 01 00)
                 |------ word 0 -------| |------ word 1 -------|
 
                 XSim / Bitstream of std::array<char, N> / std::string
                  00 01 02 03 ...                         62 63
               */
              // Here we are filling std::array<char, N>, which has reversed order
              // to std::bitset, so there is a - sign in [wordWidth - k]
              inputClock->m_signal[nAxialTSF - 1 - iTSF][iTracker][pos] =
                std_logic(ccword[j][wordWidth - k]);
            }
            // fill the TS hit
            offsetBitWidth = 82;
            for (unsigned pos = 0; pos < numTS * lenTS; ++pos) {
              const int j = (offsetBitWidth + pos + iTSF * numTS * lenTS) / wordWidth;
              const int k = (offsetBitWidth + pos + iTSF * numTS * lenTS) % wordWidth;
              dataWord word(data32tab[iFinesse_i][i + j]);
              // MSB (leftmost) in firmware -> smallest index in Bitstream's
              // std::array (due to XSIM) -> largest index in std::bitset
              // so the index is reversed in this assignment
              inputClock->m_signal[nAxialTSF - 1 - iTSF][iTracker]
              [clockCounterWidth + pos] = std_logic(word[wordWidth - 1 - k]);
            }
          } else {
            /*
              x"dddd" & (15 downto 11 => '0') & revoclk &
              cntr125M(15 downto 0) &
              (15 downto 5 => '0') & ccError &
              -- 64
              cc(4) & tsfs(4)(209 downto 0) &
              cc(3) & tsfs(3)(209 downto 0) &
              cc(2) & tsfs(2)(209 downto 0) &
              cc(1) & tsfs(1)(209 downto 0) &
              cc(0) & tsfs(0)(209 downto 0) &
            */
            // fill the cc and TS hit
            offsetBitWidth = 64;
            unsigned TSFWidth = clockCounterWidth + numTS * lenTS;
            for (unsigned pos = 0; pos < TSFWidth; ++pos) {
              const int j = (offsetBitWidth + pos + iTSF * TSFWidth) / wordWidth;
              const int k = (offsetBitWidth + pos + iTSF * TSFWidth) % wordWidth;
              dataWord word(data32tab[iFinesse_i][i + j]);
              inputClock->m_signal[nAxialTSF - 1 - iTSF][iTracker][pos] =
                std_logic(word[wordWidth - 1 - k]);
            }
          }
          if (debugLevel >= 100) {
            display_hex(inputClock->m_signal[nAxialTSF - 1 - iTSF][iTracker]);
          }
        }
        // fill output
        if (firmwareVersion < "18012600") {
          /*
            -- 1132
            Main_out(731 downto 0) &
          */
          const int outputOffset = nAxialTSF * numTS * lenTS;
          const int oldtrackWidth = 6;
          for (unsigned pos = 0; pos < 732; ++pos) {
            const int j = (offsetBitWidth + pos + outputOffset) / wordWidth;
            const int k = (offsetBitWidth + pos + outputOffset) % wordWidth;
            dataWord word(data32tab[iFinesse_i][i + j]);
            outputClock->m_signal.at(iTracker).at(clockCounterWidth + oldtrackWidth + pos)
              = std_logic(word[wordWidth - 1 - k]);
          }
        } else {
          /*
            -- 1159
            old_track(5 downto 0) &
            Main_out(731 downto 0) &
           */
          //const int outputOffset = 1159;
          const int outputOffset = offsetBitWidth +  nAxialTSF * numTS * lenTS + 45;  //1159 with numTS=10 ,  1684 with numTS=15
          for (unsigned pos = 0; pos < T2DOutputWidth; ++pos) {
            const int j = (pos + outputOffset) / wordWidth;
            const int k = (pos + outputOffset) % wordWidth;
            dataWord word(data32tab[iFinesse_i][i + j]);
            try {
              outputClock->m_signal.at(iTracker).at(clockCounterWidth + pos)
                = std_logic(word[wordWidth - 1 - k]);
            } catch (const std::out_of_range& e) {
              B2DEBUG(20, "Out-of-range access ot outputClock->m_signal.at(iTracker).at(clockCounterWidth + pos)"
                      << LogVar("iTracker", iTracker)
                      << LogVar("clockCounterWidth", clockCounterWidth)
                      << LogVar("post", pos));
              break;
            }
          }
        }
        if (debugLevel >= 100) {
          display_hex(outputClock->m_signal.at(iTracker));
        }
      }
    }

unpack() [2/2]

virtual void unpack ( int  , std::array< int *, nFinesse >  , std::array< int, nFinesse >  , bool    )

inlinevirtualinherited

Unpack the Belle2Link data and fill the Bitstream.

Reimplemented in Neuro.

Definition at line 110 of file CDCTriggerUnpackerModule.h.

                              {};

Member Data Documentation

cnttrg

int& cnttrg

inherited

counter of trgger signal, total 32 bits, the 20 LSBs recorded in the event header

Definition at line 96 of file CDCTriggerUnpackerModule.h.

debugLevel

int debugLevel

inherited

debug level in the steering file

Definition at line 99 of file CDCTriggerUnpackerModule.h.

delay

int& delay

inherited

Reference to the variable of its Belle2Link delay.

Definition at line 94 of file CDCTriggerUnpackerModule.h.

eventWidth

unsigned eventWidth

inherited

Size of an event in the Belle2Link data in 32-bit words.

Definition at line 74 of file CDCTriggerUnpackerModule.h.

firmwareType

std::string firmwareType

inherited

type of the FPGA firmware

Definition at line 90 of file CDCTriggerUnpackerModule.h.

firmwareVersion

std::string firmwareVersion

inherited

version of the FPGA firmware

Definition at line 92 of file CDCTriggerUnpackerModule.h.

headerSize

int headerSize

inherited

Size of the B2L header in words.

Definition at line 78 of file CDCTriggerUnpackerModule.h.

iFinesse

int iFinesse

inherited

FINESSE (HSLB) id) of the board.

Definition at line 82 of file CDCTriggerUnpackerModule.h.

iFinesse_pcie40

int iFinesse_pcie40

inherited

PCIe40 ch id of the board.

Definition at line 86 of file CDCTriggerUnpackerModule.h.

iNode

int iNode

inherited

COPPER id of the board.

Definition at line 80 of file CDCTriggerUnpackerModule.h.

iNode_pcie40

int iNode_pcie40

inherited

PCIe40 id of the board.

Definition at line 84 of file CDCTriggerUnpackerModule.h.

inputArrayPtr

StoreArray<TSFOutputBitStream>* inputArrayPtr

pointer to the Bitstream of 2D input

Definition at line 171 of file CDCTriggerUnpackerModule.cc.

iTracker

unsigned iTracker

ID of the 2D tracker (0 to 3)

Definition at line 175 of file CDCTriggerUnpackerModule.cc.

name

std::string name

inherited

Name of the UT3.

Definition at line 72 of file CDCTriggerUnpackerModule.h.

numTS

unsigned numTS

Number of TS sent to 2D (0 to 20)

Definition at line 177 of file CDCTriggerUnpackerModule.cc.

offset

unsigned offset

inherited

The starting point of the data in an event.

Definition at line 76 of file CDCTriggerUnpackerModule.h.

offsetBitWidth

unsigned offsetBitWidth

starting point of the input data in an Belle2Link event

Definition at line 179 of file CDCTriggerUnpackerModule.cc.

outputArrayPtr

StoreArray<T2DOutputBitStream>* outputArrayPtr

pointer to the Bitstream of 2D output to 3D/Neuro

Definition at line 173 of file CDCTriggerUnpackerModule.cc.

---

The documentation for this struct was generated from the following file:

• trg/cdc/modules/unpacker/src/CDCTriggerUnpackerModule.cc