Belle II Software  release-08-01-10
Merger.cc
1 /**************************************************************************
2  * basf2 (Belle II Analysis Software Framework) *
3  * Author: The Belle II Collaboration *
4  * *
5  * See git log for contributors and copyright holders. *
6  * This file is licensed under LGPL-3.0, see LICENSE.md. *
7  **************************************************************************/
8 
9 //-----------------------------------------------------------------------------
10 // Description : A class to represent a CDC Merger board
11 //-----------------------------------------------------------------------------
12 
13 #define TRGCDC_SHORT_NAMES
14 
15 #include <algorithm>
16 #include <iostream>
17 #include <iomanip>
18 #include "trg/trg/Debug.h"
19 #include "trg/trg/State.h"
20 #include "trg/trg/Channel.h"
21 #include "trg/cdc/TRGCDC.h"
22 #include "trg/cdc/Merger.h"
23 #include "trg/cdc/FrontEnd.h"
24 #include "trg/cdc/Wire.h"
25 
26 using namespace std;
27 
28 namespace Belle2 {
34  TRGCDCMerger::TRGCDCMerger(const std::string& name,
35  unitType type,
36  const TRGClock& systemClock,
37  const TRGClock& dataClock,
38  const TRGClock& userClockInput,
39  const TRGClock& userClockOutput)
40  : TRGBoard(name, systemClock, dataClock, userClockOutput, userClockOutput),
41  _type(type),
42  _misb(0),
43  _mosb(0)
44  {
45  userClockInput.name(); //jb
46  }
47 
49  {
50  }
51 
52  string
54  {
55  return ("TRGCDCMerger version 0.00");
56  }
57 
59  TRGCDCMerger::type(void) const
60  {
61  return _type;
62  }
63 
64 
65  int
67  ofstream& outfile)
68  {
69 
70  // string cname = "UNKNOWN";
71  // if (_type == innerType)
72  outfile << "-- inner type" << endl;
73  string cname = "TRGCDCMergerInner";
74  // }
75  // else {
76  // outfile << "-- outer type" << endl;
77  // cname = "TRGCDCMergerOuter";
78  // }
79 
80  outfile << "--" << endl;
81  outfile << endl;
82  outfile << " component " << cname << endl;
83  // int err = implementationPort(type, outfile);
84  outfile << " end component;" << endl;
85 
86  outfile << "--------------------------------------------------------------"
87  << endl;
88 
89  outfile << "entity " << cname << "is" << endl;
90  int err = implementationPort(type, outfile);
91  outfile << "end " << cname << ";" << endl;
92  outfile << endl;
93  outfile << "architecture Behavioral of " << cname << " is" << endl;
94  outfile << " -- local" << endl;
95  outfile << endl;
96  outfile << "begin" << endl;
97  outfile << "end Behavioral;" << endl;
98 
99  return err;
100  }
101 
102 
103  int
105  ofstream& outfile)
106  {
107  outfile << " port (" << endl;
108 
109  //...125MHz clock (TRG system clock)...
110  outfile << " -- 127.216MHz clock (TRG system clock)" << endl;
111  outfile << " clk : in std_logic;" << endl;
112 
113  //...Coarse timing...
114  outfile << " -- Coarse timing (counter with 127.216MHz clock)" << endl;
115  outfile << " tmc : in std_logic_vector(0 to 7);" << endl;
116 
117  //...Hit pattern...
118  outfile << " -- Hit pattern(80 bits for 80 wires)" << endl;
119  outfile << " ptn : in std_logic_vector(0 to 80);" << endl;
120 
121  //...Fine timing for each wire...
122  /*
123  outfile << " -- Fine timing within 127.216MHz clock" << endl;
124  for (unsigned i = 0; i < 80; i++) {
125  outfile << " w" << TRGUtil::itostring(i)
126  << " : in std_logic_vector(0 to 3);" << endl;
127  }
128  */
129 
130  //...Hit pattern output...
131  outfile << " -- Hit pattern output" << endl;
132  outfile << " hit : out std_logic_vector(0 to 80);" << endl;
133  outfile << " -- 4 bit fine timing for 16 priority wires" << endl;
134  outfile << " pri : out std_logic_vector(0 to 63);" << endl;
135  outfile << " -- 2 bit fine timing for the fastest hit in 16 TS" << endl;
136  outfile << " fst : out std_logic_vector(0 to 31)" << endl;
137  outfile << " );" << endl;
138 
139  return 0;
140  }
141 
142  void
144  {
145  std::vector<const TRGCDCFrontEnd*>::push_back(a);
146  }
147 
148  void
149  TRGCDCMerger::dump(const string& message, const string& pre) const
150  {
151  TRGBoard::dump(message, pre);
152  }
153 
154  void
156  {
157 
158  TRGDebug::enterStage("Merger simulattion");
159 
160  //...Clear input signal bundle...
161  if (_misb) {
162  for (unsigned i = 0; i < _misb->size(); i++)
163  delete (* _misb)[i];
164  delete _misb;
165  }
166  if (_mosb) {
167  for (unsigned i = 0; i < _mosb->size(); i++)
168  delete (* _mosb)[i];
169  delete _mosb;
170  }
171 
172  //...Clock...
173  const TRGClock& dClock = clockData();
174 
175  // ... Make input signal bundle .... ???
176  TRGSignalVector input(name() + "inputFrontEnds", dClock);
177  const string ni = name() + "InputSignalBundle";
178  _misb = new TRGSignalBundle(ni, dClock);
179 
180 
181  // Input from FrontEnds
182  // const unsigned nFrontEnds = size();
183 
184  // TRGSignalBundle* testin = ((*this)[0])->_osb;
185  // TRGSignalBundle testin2 = new TRGSignalBundle( ((*this)[0])->output() );
186  //TRGSignalBundle * testin = new TRGSignalBundle * ((*this)[0]->output());
187  //TRGSignalVector * input1 = new TRGSignalVector ( *(((*this)[0]->_osb)[0])[0] ),
188  // * input2 = new TRGSignalVector ( *(((*this)[1]->_osb)[0])[0] );
189 
190 
191  // _osb in FrontEnd.h is private, use getOSB() to get input bundle.
192  TRGSignalVector* input1 = new TRGSignalVector(*((*(*this)[0]->getOSB())[0]));
193  TRGSignalVector* input2 = new TRGSignalVector(*((*(*this)[1]->getOSB())[0]));
194 
195 
196  for (unsigned s = 0; s < input1->size(); s++) {
197  TRGSignal ws = (*input1)[s];
198  input += ws;
199  }
200  for (unsigned s = 0; s < input2->size(); s++) {
201  TRGSignal ws = (*input2)[s];
202  input += ws;
203  }
204 
205  //...Create FrontEnd output data
206  TRGSignalVector* fedata = new TRGSignalVector(input);
207  fedata->clock(dClock);
208  fedata->name(name() + "@dataClock");
209  _misb->push_back(fedata);
210 
211 // cout<<"Merger input start"<<endl;
212 // _misb->dump("detail", TRGDebug::tab());
213 // cout<<"Merger input end"<<endl;
214 
215  //...Data clock...
216  // Data clock position data is omitted. Is this problem?
217 
218  //...Make output signal bundle...
219  const string no = name() + "OutSigBundle";
220  if (type() == innerType) {
221  _mosb = new TRGSignalBundle(no,
222  dClock,
223  * _misb,
224  256,
225  TCMerger::packerInner);
226  } else if (type() == outerType) {
227  _mosb = new TRGSignalBundle(no,
228  dClock,
229  * _misb,
230  256,
231  TCMerger::packerOuter);
232  }
233  mosb = _mosb;
234 
235  if (TRGCDC::getTRGCDC()->firmwareSimulationMode() & 0x2)
236  mosb->dumpCOE("",
237  TRGCDC::getTRGCDC()->firmwareSimulationStartDataClock(),
238  TRGCDC::getTRGCDC()->firmwareSimulationStopDataClock());
239 
240  //...Output to a channel...
241  output(0)->signal(_mosb);
242 
243  // Terminate
244  delete input1;
245  delete input2;
246 
247  if (TRGDebug::level() > 1) {
248  _misb->dump("", TRGDebug::tab());
249  _mosb->dump("", TRGDebug::tab());
250  }
251 
252  TRGDebug::leaveStage("Merger simulattion");
253  }
254 
255 
256  TRGState
258  {
259 
260  //...inputInsdie should be 32 hit pattern and 2x16x5 timing, total 192 bits...
261  // plus edge information
262  //
263  // Wire numbers and TS ID
264  //
265  // outside
266  //
267  // +--+--+--+--+- -+--+--+--+--+--+--+
268  // | 79 | 78 | .... | 66 | 65 | 64 |
269  // +--+--+--+--+--+- -+--+--+--+--+--+--+
270  // | 63 | 62 | ..... | 50 | 49 | 48 |
271  // +--+--+--+--+--+- -+--+--+--+--+--+--+
272  // | 47 | 46 | .... | 34 | 33 | 32 |
273  // +--+--+--+--+- -+--+--+--+--+--+--+
274  //
275  // +--+--+--+--+- -+--+--+--+--+--+--+
276  // | 31 | 30 | .... | 18 | 17 | 16 |
277  // +--+--+--+--+--+- -+--+--+--+--+--+--+
278  // | 15 | 14 | ..... | 2 | 1 | 0 |
279  // +--+--+--+--+--+- -+--+--+--+--+--+--+
280  // | x | x | .... | x | x | x |
281  // +--+--+--+--+- -+--+--+--+--+--+--+
282  //
283  // 15 14 .... 2 1 0 <- partial TS ID, aligned with the 2nd row
284  //
285  // inside
286  //
287  //...Prepare a state for output...
288  // hit map: 80x1
289  // priority hit time: 16x4
290  // fastest hit time: 16x4
291  // 2nd proi. hit flag: 16x1
292  // edge time info: 5x4
293  // cc: 1x9
294  // N/A and reserved: fill to total 256 bits
295 
296  TRGState s(80 + 16 * 4 + 16 * 4 + 16 + 5 * 4 + 1 * 9 + 3); // fill to 256 bits
297 
298  //...Set up bool array...
299  bool* binput = new bool[input.size()];
300  input.copy2bool(binput);
301  bool* binside = & binput[0];
302  bool* boutside = & binput[256]; // half of the input.size(), should be 256
303 
304 
305  // ... hitmap ...
306  const bool* const hitptn0 = & binside[0]; // 16x2 = 32 bits
307  const bool* const hitptn1 = & boutside[0]; // 16x3 = 48 bits
308  s.set(0, 32, hitptn0);
309  s.set(32, 48, hitptn1);
310  unsigned p = 80;
311 
312  bool PTS_in_hit[16];
313  bool PTS_out_hit[16];
314  for (unsigned i = 0; i < 16; i++) {
315  if (i == 0) {
316  PTS_in_hit[i] = hitptn0[0] || hitptn0[16];
317  PTS_out_hit[i] = hitptn1[0] || hitptn1[1] || hitptn1[16] || hitptn1[17] || hitptn1[32] || hitptn1[33] || hitptn1[34];
318  } else if (i == 1) {
319  PTS_in_hit[i] = hitptn0[1] || hitptn0[16] || hitptn0[17];
320  PTS_out_hit[i] = hitptn1[0] || hitptn1[1] || hitptn1[2] || hitptn1[16] || hitptn1[17] || hitptn1[18] || hitptn1[32] || hitptn1[33]
321  || hitptn1[34] || hitptn1[35];
322  } else if (i == 14) {
323  PTS_in_hit[i] = hitptn0[14] || hitptn0[29] || hitptn0[30];
324  PTS_out_hit[i] = hitptn1[13] || hitptn1[14] || hitptn1[15] || hitptn1[28] || hitptn1[29] || hitptn1[30] || hitptn1[31]
325  || hitptn1[44] || hitptn1[45] || hitptn1[46] || hitptn1[47];
326  } else if (i == 15) {
327  PTS_in_hit[i] = hitptn0[15] || hitptn0[30] || hitptn0[31];
328  PTS_out_hit[i] = hitptn1[14] || hitptn1[15] || hitptn1[29] || hitptn1[30] || hitptn1[31] || hitptn1[45] || hitptn1[46]
329  || hitptn1[47];
330  } else {
331  PTS_in_hit[i] = hitptn0[i] || hitptn0[i + 15] || hitptn0[i + 16];
332  PTS_out_hit[i] = hitptn1[i - 1] || hitptn1[i] || hitptn1[i + 1] || hitptn1[i + 14] || hitptn1[i + 15] || hitptn1[i + 16]
333  || hitptn1[i + 17] || hitptn1[i + 30] || hitptn1[i + 31] || hitptn1[i + 32] || hitptn1[i + 33] || hitptn1[i + 34];
334  }
335  }
336 
337 
338  // ... priority time ... and 2nd priority location .... already prepared in FrontEnd packer
339  const bool* const pt[16] = {
340  &binside[33], &binside[38], &binside[43], &binside[48],
341  &binside[53], &binside[58], &binside[63], &binside[68],
342  &binside[73], &binside[78], &binside[83], &binside[88],
343  &binside[93], &binside[98], &binside[103], &binside[108]
344  };
345 
346  for (unsigned i = 0; i < 16; i++) {
347  s.set(p, 4, pt[i]);
348  p += 4;
349  }
350 
351  // ... fastest time ...
352  const bool* const ftinside[16] = {
353  &binside[128], &binside[133], &binside[138], &binside[143],
354  &binside[148], &binside[153], &binside[158], &binside[163],
355  &binside[168], &binside[173], &binside[178], &binside[183],
356  &binside[188], &binside[193], &binside[198], &binside[203]
357  };
358  const bool* const ftoutside[16] = {
359  &boutside[48], &boutside[53], &boutside[58], &boutside[63],
360  &boutside[68], &boutside[73], &boutside[78], &boutside[83],
361  &boutside[88], &boutside[93], &boutside[98], &boutside[103],
362  &boutside[108], &boutside[113], &boutside[118], &boutside[123]
363  };
364 
365 
366  // need to consider if that area is hit
367  for (unsigned i = 0; i < 16; i++) {
368  TRGState st[2];
369  st[0] = TRGState(5, ftinside[i]);
370  st[1] = TRGState(5, ftoutside[i]);
371  if (!PTS_in_hit[i]) st[0].set(5, true);
372  if (!PTS_out_hit[i]) st[1].set(5, true);
373 
374  if (PTS_in_hit[i] || PTS_out_hit[i]) {
375  if (st[0] < st[1]) {
376  s.set(p, 4, &binside[129 + i * 5]);
377  } else {
378  s.set(p, 4, &boutside[49 + i * 5]);
379  }
380  } else {
381  }
382  p += 4;
383  }
384 
385  // ... 2nd priority location ...
386  s.set(p, 16, &binside[112]);
387  p += 16;
388 
389  // ... edge information ...
390 
391  if (hitptn0[31]) {
392  s.set(p, 4, &binside[209]); // 4-bit hit time of cell[31]
393  } else {
394  }
395  p += 4;
396 
397 
398  if (hitptn1[32]) {
399  s.set(p, 4, &boutside[129]); // 4-bit hit time of cell[64]
400  } else {
401  }
402  p += 4;
403 
404 
405  if (hitptn1[0] || hitptn1[16] || hitptn1[32] || hitptn1[33]) {
406  s.set(p, 4, &boutside[134]); // edge info. purely from outside FE. cell 32, 48, 64, 65
407  } else {
408  }
409  p += 4;
410 
411 
412 
413  TRGState et[2]; // edge info. from both FE, cell 31 and 47, 62, 63, 78, 79
414  et[0] = TRGState(5, &binside[208]);
415  et[1] = TRGState(5, &boutside[138]);
416 
417  if ((!hitptn1[15]) && (!hitptn1[30]) && (!hitptn1[31]) && (!hitptn1[46]) && (!hitptn1[47])) et[1].set(5, true);
418  if ((!hitptn0[31])) et[0].set(5, true);
419 
420  if (hitptn0[31] || hitptn1[15] || hitptn1[30] || hitptn1[31] || hitptn1[46] || hitptn1[47]) {
421  if (et[0] < et[1]) {
422  s.set(p, 4, &binside[209]);
423  } else {
424  s.set(p, 4, &boutside[139]);
425  }
426  } else {
427  }
428 
429  p += 4;
430 
431 
432 
433  if (hitptn1[31] || hitptn1[47]) {
434  s.set(p, 4, &boutside[144]); // edge info. purely from outside FE. cell 63, 79
435  } else {
436  }
437 //p+=4;
438 
439  // ...clock counter ...
440  // no process for cc at this moment
441 
442  // ...N/A and reserved bit ...
443  // no process for these at this moment
444 
445 //...Debug...
446  if (TRGDebug::level() > 1) {
447  unpackerInner(input, s);
448  }
449 
450 //...Termination...
451  delete[] binput;
452 
453  return s;
454  }
455 
456 
457 
458 
459  TRGState
461  {
462 
463  // packerOuter: for SuperLayer 1 - 8
464  //
465  // inputInsdie should be 48 hit pattern and 1x16x5 + 1x16x5 timing,
466  // plus edge information
467  // total 192 bits... (whole data pack 256 bits)
468  //
469  // inputOutside should be 48 hit pattern and 1x16x5 + 1x16x5 timing,
470  // plus edge information
471  // total 192 bits... (whole data pack 256 bits)
472  //
473  // Wire numbers and TS ID
474  //
475  // Outside
476  //
477  // +--+--+--+--+- -+--+--+--+--+--+--+
478  // | x | x | .... | x | x | x |
479  // +--+--+--+--+--+- -+--+--+--+--+--+--+
480  // | 79 | 78 | ..... | 66 | 65 | 64 |
481  // +--+--+--+--+--+- -+--+--+--+--+--+--+
482  // | 63 | 62 | .... | 50 | 49 | 48 |
483  // +--+--+--+--+--+- -+--+--+--+--+--+
484  //
485  // +--+--+--+--+- -+--+--+--+--+--+--+
486  // | 47 | 46 | .... | 34 | 33 | 32 |
487  // +--+--+--+--+--+- -+--+--+--+--+--+--+
488  // | 31 | 30 | ..... | 18 | 17 | 16 |
489  // +--+--+--+--+--+- -+--+--+--+--+--+--+
490  // | 15 | 14 | .... | 2 | 1 | 0 |
491  // +--+--+--+--+- -+--+--+--+--+--+--+
492  //
493  // 15 14 .... 2 1 0 <- partial TS ID
494  //
495  //...Prepare a state for output...
496  // hit map: 80x1
497  // priority hit time: 16x4
498  // fastest hit time: 16x4
499  // 2nd proi. hit flag: 16x1
500  // edge time info: 3x4
501  // cc: 1x9
502  // N/A and reserved: fill to total 256 bits
503  TRGState s(80 + 16 * 4 + 16 * 4 + 16 + 3 * 4 + 9 + 11);
504 
505 
506  bool* binput = new bool[input.size()];
507  input.copy2bool(binput);
508  bool* binside = & binput[0];
509  bool* boutside = & binput[256]; // half of the input.size(), should be 256
510 
511 
512  // ... hitmap ...
513  const bool* const hitptn0 = & binside[0]; // 16x3 = 48 bits
514  const bool* const hitptn1 = & boutside[0]; // 16x2 = 32 bits
515  s.set(0, 48, hitptn0);
516  s.set(48, 32, hitptn1);
517 
518  bool PTS_in_hit[16];
519  bool PTS_out_hit[16];
520  for (unsigned i = 0; i < 16; i++) {
521  if (i == 0) {
522  PTS_in_hit[i] = hitptn0[0] || hitptn0[1] || hitptn0[16] || hitptn0[32] ;
523  PTS_out_hit[i] = hitptn1[0] || hitptn1[16] || hitptn1[17];
524  } else if (i == 15) {
525  PTS_in_hit[i] = hitptn0[14] || hitptn0[15] || hitptn0[30] || hitptn0[31] || hitptn0[47] ;
526  PTS_out_hit[i] = hitptn1[14] || hitptn1[15] || hitptn1[30] || hitptn1[31];
527  } else {
528  PTS_in_hit[i] = hitptn0[i - 1] || hitptn0[i] || hitptn0[i + 1] || hitptn0[i + 15] || hitptn0[i + 16] || hitptn0[i + 32];
529  PTS_out_hit[i] = hitptn1[i - 1] || hitptn1[i] || hitptn1[i + 15] || hitptn1[i + 16] || hitptn1[i + 17];
530  }
531  }
532 
533  // ... priority time ...
534  /*
535  const bool * const ptinside[16] = {
536  &binside[49], &binside[54], &binside[59], &binside[64],
537  &binside[69], &binside[74], &binside[79], &binside[84],
538  &binside[89], &binside[94], &binside[99], &binside[104],
539  &binside[109], &binside[114], &binside[119], &binside[124]
540  };
541  const bool * const ptoutside[16] = {
542  &boutside[49], &boutside[54], &boutside[59], &boutside[64],
543  &boutside[69], &boutside[74], &boutside[79], &boutside[84],
544  &boutside[89], &boutside[94], &boutside[99], &boutside[104],
545  &boutside[109], &boutside[114], &boutside[119], &boutside[124]
546  };
547  */
548 
549  // i = 0...15
550  // inside binside[31+i]
551  // outside boutside[i]
552 // const bool scflag[2] = {false, true};
553  const bool dummy[6] = {false, false, false, false, false, true};
554  const TRGState stDummy(6, dummy);
555  unsigned p = 80;
556 
557  for (unsigned i = 0; i < 16; i++) {
558  //unsigned sc=0;
559  if (hitptn0[32 + i]) {
560  s.set(p, 4, &binside[49 + 5 * i]);;
561  } else {
562  // decide which 2nd priority time to use if 1st priority cell not hit
563  TRGState st[2];
564  if (i == 0) {
565  if (hitptn1[0]) {
566  s.set(p, 4, &boutside[49]);
567 // sc = 1;
568  s.set(208 + i, 1, true);
569  } else {
570 // sc = 0;
571 // s.set(209+i, 1, &scflag[sc]);
572  }
573  } else {
574  st[0] = TRGState(5, &boutside[43 + i * 5]);
575  st[1] = TRGState(5, &boutside[48 + i * 5]);
576  if (!hitptn1[i - 1]) st[0].set(5, true);
577  if (!hitptn1[i]) st[1].set(5, true);
578 
579  if (hitptn1[i] || hitptn1[i - 1]) {
580  if (st[1] < st[0]) {
581  s.set(p, 4, &boutside[49 + i * 5]);
582  s.set(208 + i, 1, true); // only set scflag to true when left is it and also faster
583  } else {
584 // sc = 1;
585  s.set(p, 4, &boutside[44 + i * 5]);
586  }
587  } else {
588  }
589 
590 
591  }
592 
593  }
594 // s.set(209+i, 1, &scflag[sc]); //the scflag is only consider when (1st not hit) && (2nd is hit)
595  p += 4;
596  }
597 
598 
599  // ... fastest time ...
600 
601 
602 
603 
604  /*
605  const bool * const ftinside[16] = {
606  &binside[129], &binside[134], &binside[139], &binside[144],
607  &binside[149], &binside[154], &binside[159], &binside[164],
608  &binside[169], &binside[174], &binside[179], &binside[184],
609  &binside[189], &binside[194], &binside[199], &binside[204]
610  };
611  const bool * const ftoutside[16] = {
612  &boutside[129], &boutside[134], &boutside[139], &boutside[144],
613  &boutside[149], &boutside[154], &boutside[159], &boutside[164],
614  &boutside[169], &boutside[174], &boutside[179], &boutside[184],
615  &boutside[189], &boutside[194], &boutside[199], &boutside[204]
616  };
617  */
618  // need to consider if those areas are hit
619  p = 144;
620  for (unsigned i = 0; i < 16; i++) {
621  TRGState st[2];
622  st[0] = TRGState(5, &binside[128 + i * 5]);
623  st[1] = TRGState(5, &boutside[128 + i * 5]);
624 
625  if (!PTS_in_hit[i]) st[0].set(5, true);
626  if (!PTS_out_hit[i]) st[1].set(5, true);
627 
628  if (PTS_in_hit[i] || PTS_out_hit[i]) {
629  if (st[0] < st[1]) {
630  s.set(p, 4, &binside[129 + i * 5]);
631  } else {
632  s.set(p, 4, &boutside[129 + i * 5]);
633  }
634  } else {
635  }
636  /*
637  if ( st[0] < st[1] ) {
638  s.set(p, 4, &binside[129 + i*5]);
639  }
640  else {
641  s.set(p, 4, &boutside[129 + i*5]);
642  }
643  */
644 
645  p += 4;
646  }
647 
648  // ... edge information ...
649  /*
650  const bool * const etinside[16] = {&binside[209], &binside[214] };
651  const bool * const etoutside[16] = {&boutside[209], &boutside[214] };
652  */
653  p = 224;
654 
655  if (hitptn1[15]) {
656  s.set(p, 4, &boutside[124]); // 4-bit hit time of cell[63]
657  }
658 
659  for (unsigned i = 0; i < 2; i++) {
660  TRGState et[2];
661  // need to consider if the two areas hit
662  et[0] = TRGState(5, &binside[208 + i * 5]);
663  et[1] = TRGState(5, &boutside[208 + i * 5]);
664 
665  if (i == 0) {
666  if (!hitptn0[0]) et[0].set(5, true);
667  if (!hitptn1[16]) et[1].set(5, true);
668  p += 4;
669  if (hitptn0[0] || hitptn1[16]) {
670  if (et[0] < et[1]) {
671  s.set(p, 4, &binside[209 + i * 5]);
672  } else {
673  s.set(p, 4, &boutside[209 + i * 5]);
674  }
675  } else {
676  }
677 
678  } else if (i == 1) {
679  if (!hitptn0[15] && !hitptn0[31]) et[0].set(5, true);
680  if (!hitptn1[15] && !hitptn1[31]) et[1].set(5, true);
681  p += 4;
682  if (hitptn0[15] || hitptn0[31] || hitptn1[15] || hitptn1[31]) {
683  if (et[0] < et[1]) {
684  s.set(p, 4, &binside[209 + i * 5]);
685  } else {
686  s.set(p, 4, &boutside[209 + i * 5]);
687  }
688  } else {
689  }
690 
691 
692  }
693  // p += 4;
694  } // warning, here 'p' is at the beginning position of the last sensible data
695 
696 
697  // ...clock counter ...
698  // no process for cc at this moment
699 
700  // ...N/A and reserved bit ...
701  // no process for these at this moment
702 
703 
704 //...Debug...
705  if (TRGDebug::level() > 1) {
706  unpackerOuter(input, s);
707  }
708 
709 //...Termination...
710  delete[] binput;
711  return s;
712 
713  }
714 
715 
716 
717 
718  void
720  const TRGState& output)
721  {
722 
723  TRGState inputInside = input.subset(0, 256);
724  TRGState inputOutside = input.subset(256, 256);
725 
726  unsigned ipos = 0, o = 0;
727 
728  cout << "======================= Merger unpackerInner ================================= " << endl;
729  cout << "input bit information: " << endl;
730  for (unsigned bi = 0; bi < input.size(); bi++) {
731  if (input[bi]) cout << "* " ;
732  else cout << ". ";
733  if ((bi % 16) == 15) cout << endl;
734  if (bi == 255) cout << "--------------------------------" << endl;
735  }
736 
737  cout << "Input bit size = " << input.size() << " and Output bit size =" << output.size() << endl << endl;
738 
739  cout << "Hit map: " << endl;
740  cout << "inputOutside : wire hit pattern" << endl;
741  cout << " ";
742  for (unsigned i = 0; i < 48; i++) {
743  const unsigned j = 47 - i;
744  if (i && ((i % 8) == 0))
745  cout << "_";
746  if (inputOutside[j])
747  cout << "*";
748  else
749  cout << ".";
750  }
751  cout << endl;
752  cout << "inputInside : wire hit pattern" << endl;
753  cout << " ";
754  for (unsigned i = 0; i < 32; i++) {
755  const unsigned j = 31 - i;
756  if (i && ((i % 8) == 0))
757  cout << "_";
758  if (inputInside[j])
759  cout << "*";
760  else
761  cout << ".";
762  }
763  cout << endl;
764  cout << "-------------------------------------------" << endl;
765  cout << "Output : wire hit pattern" << endl;
766  cout << " ";
767  for (unsigned i = 0; i < 80; i++) {
768  const unsigned j = 79 - i;
769  if ((i % 16) == 0) {
770  cout << endl << " ";
771  if (int(i / 16) % 2) {
772  } else cout << " ";
773  }
774  if (output[j])
775  cout << "O ";
776  else
777  cout << ". ";
778  }
779  cout << endl;
780  cout << " -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-" << endl << endl;
781 
782  cout << "Priority cell timing:" << endl;
783  cout << "inputOutside : no priority cell timing information" << endl;
784  cout << "inputInside : priority cell timing" << endl;
785  ipos = 32;
786  for (unsigned i = 0; i < 16; i++) {
787  TRGState s = inputInside.subset(ipos + i * 5, 5);
788  if ((i % 4) == 0)
789  cout << " ";
790  cout << setw(2) << i << ": " << s << " ";
791  if ((i % 4) == 3)
792  cout << endl;
793  }
794  cout << "inputInsidepriority cell location flag" << endl;
795  ipos = 112;
796  for (unsigned i = 0; i < 16; i++) {
797  if ((i % 4) == 0)
798  cout << " ";
799  if (inputInside[ipos + i])
800  cout << setw(2) << i << ": (1)Left ";
801  else
802  cout << setw(2) << i << ": (0)Right ";
803  if ((i % 4) == 3)
804  cout << endl;
805  }
806 
807  cout << "ouput : priority cell timing" << endl;
808  o = 80;
809  for (unsigned i = 0; i < 16; i++) {
810  TRGState s = output.subset(o + i * 4, 4);
811  if ((i % 4) == 0)
812  cout << " ";
813  cout << setw(2) << i << ": " << s << " ";
814  if ((i % 4) == 3)
815  cout << endl;
816  }
817  cout << "output : priority cell location flag" << endl;
818  o = 208;
819  for (unsigned i = 0; i < 16; i++) {
820  if ((i % 4) == 0)
821  cout << " ";
822  if (output[o + i])
823  cout << setw(2) << i << ": (1)Left ";
824  else
825  cout << setw(2) << i << ": (0)Right ";
826  if ((i % 4) == 3)
827  cout << endl;
828  }
829  cout << " -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
830 
831  cout << "Fastest timing of each TrackSegment: " << endl;
832  cout << "inputOutside : fastest timing" << endl;
833  ipos = 128;
834  for (unsigned i = 0; i < 16; i++) {
835  TRGState s = inputOutside.subset(ipos + i * 5, 5);
836  if ((i % 4) == 0)
837  cout << " ";
838  cout << setw(2) << i << ": " << s << " ";
839  if ((i % 4) == 3)
840  cout << endl;
841  }
842  ipos = 48;
843  cout << "inputInside : fastest timing" << endl;
844  for (unsigned i = 0; i < 16; i++) {
845  TRGState s = inputInside.subset(ipos + i * 5, 5);
846  if ((i % 4) == 0)
847  cout << " ";
848  cout << setw(2) << i << ": " << s << " ";
849  if ((i % 4) == 3)
850  cout << endl;
851  }
852  cout << "output : fastest timing" << endl;
853  o = 144;
854  for (unsigned i = 0; i < 16; i++) {
855  TRGState s = output.subset(o + i * 4, 4);
856  if ((i % 4) == 0)
857  cout << " ";
858  cout << setw(2) << i << ": " << s << " ";
859  if ((i % 4) == 3)
860  cout << endl;
861  }
862  cout << " -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
863 
864  cout << "Edge time information: " << endl;
865  cout << "inputOutside : timing of missing wires" << endl;
866  ipos = 128;
867  for (unsigned i = 0; i < 4; i++) {
868  TRGState s = inputOutside.subset(ipos + i * 5, 5);
869  if ((i % 4) == 0)
870  cout << " ";
871  cout << setw(2) << i << ": " << s << " ";
872  if ((i % 4) == 3)
873  cout << endl;
874  } cout << endl;
875  ipos = 208;
876  cout << "inputInside : timing of missing wires" << endl;
877  for (unsigned i = 0; i < 1; i++) {
878  TRGState s = inputInside.subset(ipos + i * 5, 5);
879  if ((i % 4) == 0)
880  cout << " ";
881  cout << setw(2) << i << ": " << s << " ";
882  if ((i % 4) == 3)
883  cout << endl;
884  } cout << endl;
885  cout << "output : timing of missing wires" << endl;
886  o = 224;
887  for (unsigned i = 0; i < 5; i++) {
888  TRGState s = output.subset(o + i * 4, 4);
889  if ((i % 4) == 0)
890  cout << " ";
891  cout << setw(2) << i << ": " << s << " ";
892  if ((i % 4) == 3)
893  cout << endl;
894  }
895  cout << endl;
896 
897  cout << "================== End of Merger unpackerInner ========================= " << endl;
898 
899 
900  }
901 
902 
903 
904  void
906  const TRGState& output)
907  {
908 
909  TRGState inputInside = input.subset(0, 256);
910  TRGState inputOutside = input.subset(256, 256);
911 
912  unsigned o = 0;
913 
914  cout << "======================= Merger unpackerOuter================================== " << endl;
915  cout << "input bit information: " << endl;
916  for (unsigned bi = 0; bi < input.size(); bi++) {
917  if (input[bi]) cout << "* " ;
918  else cout << ". ";
919  if ((bi % 16) == 15) cout << endl;
920  if (bi == 255) cout << "--------------------------------" << endl;
921  }
922 
923  cout << "Input bit size = " << input.size() << " and Output bit size =" << output.size() << endl << endl;
924 
925  cout << "Hit map: " << endl;
926  cout << "inputOutside : wire hit pattern" << endl;
927  cout << " ";
928  for (unsigned i = 0; i < 48; i++) {
929  const unsigned j = 47 - i;
930  if (i && ((i % 8) == 0))
931  cout << "_";
932  if (inputOutside[j])
933  cout << "*";
934  else
935  cout << ".";
936  }
937  cout << endl;
938  cout << "inputInside : wire hit pattern" << endl;
939  cout << " ";
940  for (unsigned i = 0; i < 48; i++) {
941  const unsigned j = 48 - i - 1;
942  if (i && ((i % 8) == 0))
943  cout << "_";
944  if (inputInside[j])
945  cout << "*";
946  else
947  cout << ".";
948  }
949  cout << endl;
950  cout << "-------------------------------------------" << endl;
951  cout << "Output : wire hit pattern" << endl;
952  cout << " ";
953  for (unsigned i = 0; i < 80; i++) {
954  const unsigned j = 79 - i;
955  /*
956  if (i && ((i % 8) == 0))
957  cout << "_";
958  if (output[j])
959  cout << "* ";
960  else
961  cout << ". ";
962  if ( (i % 32) == 31 ) cout << endl << " ";
963  */
964  if ((i % 16) == 0) {
965  cout << endl << " ";
966  if (int(i / 16) % 2) {
967  } else cout << " ";
968  }
969  if (output[j])
970  cout << "O ";
971  else
972  cout << ". ";
973  // if ( (i % 32) == 31 ) cout << endl << " ";
974  }
975  cout << endl;
976  cout << " -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-" << endl << endl;
977 
978  cout << "Priority cell timing:" << endl;
979  cout << "inputOutside : priority cell timing" << endl;
980  o = 48;
981  for (unsigned i = 0; i < 16; i++) {
982  TRGState s = inputOutside.subset(o + i * 5, 5);
983  if ((i % 4) == 0)
984  cout << " ";
985  cout << setw(2) << i << ": " << s << " ";
986  if ((i % 4) == 3)
987  cout << endl;
988  }
989  cout << "inputInside : priority cell timing" << endl;
990  for (unsigned i = 0; i < 16; i++) {
991  TRGState s = inputInside.subset(o + i * 5, 5);
992  if ((i % 4) == 0)
993  cout << " ";
994  cout << setw(2) << i << ": " << s << " ";
995  if ((i % 4) == 3)
996  cout << endl;
997  }
998  cout << "ouput : priority cell timing" << endl;
999  o = 80;
1000  for (unsigned i = 0; i < 16; i++) {
1001  TRGState s = output.subset(o + i * 4, 4);
1002  if ((i % 4) == 0)
1003  cout << " ";
1004  cout << setw(2) << i << ": " << s << " ";
1005  if ((i % 4) == 3)
1006  cout << endl;
1007  }
1008  cout << "output : priority cell location flag" << endl;
1009  o = 208;
1010  for (unsigned i = 0; i < 16; i++) {
1011  if ((i % 4) == 0)
1012  cout << " ";
1013  if (output[o + i])
1014  cout << setw(2) << i << ": (1)Left ";
1015  else
1016  cout << setw(2) << i << ": (0)Right ";
1017  if ((i % 4) == 3)
1018  cout << endl;
1019  }
1020  cout << " -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
1021 
1022  cout << "Fastest timing of each TrackSegment: " << endl;
1023  cout << "inputOutside : fastest timing" << endl;
1024  o = 128;
1025  for (unsigned i = 0; i < 16; i++) {
1026  TRGState s = inputOutside.subset(o + i * 5, 5);
1027  if ((i % 4) == 0)
1028  cout << " ";
1029  cout << setw(2) << i << ": " << s << " ";
1030  if ((i % 4) == 3)
1031  cout << endl;
1032  }
1033  cout << "inputInside : fastest timing" << endl;
1034  for (unsigned i = 0; i < 16; i++) {
1035  TRGState s = inputInside.subset(o + i * 5, 5);
1036  if ((i % 4) == 0)
1037  cout << " ";
1038  cout << setw(2) << i << ": " << s << " ";
1039  if ((i % 4) == 3)
1040  cout << endl;
1041  }
1042  cout << "output : fastest timing" << endl;
1043  o = 144;
1044  for (unsigned i = 0; i < 16; i++) {
1045  TRGState s = output.subset(o + i * 4, 4);
1046  if ((i % 4) == 0)
1047  cout << " ";
1048  cout << setw(2) << i << ": " << s << " ";
1049  if ((i % 4) == 3)
1050  cout << endl;
1051  }
1052  cout << " -=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=-=+=-=+=-=" << endl << endl;
1053 
1054  cout << "Edge time information: " << endl;
1055  cout << "inputOutside : timing of missing wires" << endl;
1056  o = 208;
1057  for (unsigned i = 0; i < 2; i++) {
1058  TRGState s = inputOutside.subset(o + i * 5, 5);
1059  if ((i % 4) == 0)
1060  cout << " ";
1061  cout << setw(2) << i << ": " << s << " ";
1062  if ((i % 4) == 3)
1063  cout << endl;
1064  } cout << endl;
1065  cout << "inputInside : timing of missing wires" << endl;
1066  for (unsigned i = 0; i < 2; i++) {
1067  TRGState s = inputInside.subset(o + i * 5, 5);
1068  if ((i % 4) == 0)
1069  cout << " ";
1070  cout << setw(2) << i << ": " << s << " ";
1071  if ((i % 4) == 3)
1072  cout << endl;
1073  } cout << endl;
1074  cout << "output : timing of missing wires" << endl;
1075  o = 224;
1076  for (unsigned i = 0; i < 3; i++) {
1077  TRGState s = output.subset(o + i * 4, 4);
1078  if ((i % 4) == 0)
1079  cout << " ";
1080  cout << setw(2) << i << ": " << s << " ";
1081  if ((i % 4) == 3)
1082  cout << endl;
1083  }
1084  cout << endl;
1085 
1086  cout << "================= End of Merger unpackerOuter ========================= " << endl;
1087 
1088 
1089  }
1090 
1091  void //Dump all the details of _mosb into a .log file, do it in the end of simulate()
1093  {
1094  if (type() == innerType) {
1095  dump_log_inner();
1096  } else {
1097  dump_log_outer();
1098  }
1099  }
1100 
1101  void
1103  {
1104 
1105  const TRGClock& dClock = TRGCDC::getTRGCDC()->dataClock();
1106  ofstream output((name() + ".log").c_str());
1107 
1108  output << "Inner Superlayer Merger output dump" << endl << endl;
1109 
1110  const std::vector<int> changetime = _mosb->stateChanges();
1111  std::vector<vector<int>> boolvector(changetime.size());
1112  for (unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1113 
1114  for (unsigned b = 0; b < (* _mosb)[0]->size(); b++) {
1115  boolvector[ch_t].push_back(((* _mosb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1116  }
1117 
1118  output << "# of clk: " << changetime[ch_t] << " (" << dClock.absoluteTime(changetime[ch_t]) << " ns), signal vector: " << endl;
1119 
1120  output << "Hitmap: " << endl << " ";
1121  for (int b = 0; b < 80; b++) {
1122  output << boolvector[ch_t][79 - b] << " ";
1123  if (b == 15) output << endl;
1124  else if (b == 31) output << endl << " ";
1125  else if (b == 47) output << endl ;
1126  else if (b == 63) output << endl << " ";
1127  }
1128  output << endl;
1129 
1130  for (int b = 0; b < 16; b++) {
1131  output << "PT#" << b << ": " << boolvector[ch_t][ 80 + 4 * b + 3 ] << boolvector[ch_t][ 80 + 4 * b + 2 ] << boolvector[ch_t][ 80 + 4
1132  * b + 1 ]
1133  << boolvector[ch_t][ 80 + 4 * b ] << endl;
1134  }
1135  output << endl;
1136 
1137  for (int b = 0; b < 16; b++) {
1138  output << "FT#" << b << ": " << boolvector[ch_t][ 144 + 4 * b + 3 ] << boolvector[ch_t][ 144 + 4 * b + 2 ] << boolvector[ch_t][ 144
1139  + 4 * b + 1 ]
1140  << boolvector[ch_t][ 144 + 4 * b ] << endl;
1141  }
1142 
1143  output << "Secondary: " << endl;
1144  for (int b = 0; b < 16; b++) {
1145  output << boolvector[ch_t][ 223 - b ] ;
1146  }
1147 
1148  output << endl;
1149  output << "ET#0(31): " << endl << boolvector[ch_t][227] << boolvector[ch_t][226] << boolvector[ch_t][225] << boolvector[ch_t][224]
1150  << endl;
1151  output << "ET#1(64(out32)): " << endl << boolvector[ch_t][231] << boolvector[ch_t][230] << boolvector[ch_t][229] <<
1152  boolvector[ch_t][228]
1153  << endl;
1154  output << "ET#2(32, 48, 64, 65(outside 0, 16, 32, 33)): " << endl << boolvector[ch_t][235] << boolvector[ch_t][234] <<
1155  boolvector[ch_t][233]
1156  << boolvector[ch_t][232] << endl;
1157  output << "ET#3(31, 47, 62, 63, 78, 79(inside 31, outside 15, 30, 31, 46, 47)): " << endl << boolvector[ch_t][239] <<
1158  boolvector[ch_t][238]
1159  << boolvector[ch_t][237] << boolvector[ch_t][236] << endl;
1160  output << "ET#4(63, 79(outside 31, 47)): " << endl << boolvector[ch_t][243] << boolvector[ch_t][242] << boolvector[ch_t][241]
1161  << boolvector[ch_t][240] << endl;
1162 
1163 
1164 
1165  output << endl;
1166  }
1167 
1168  output.close();
1169 
1170  }
1171 
1172  void
1174  {
1175 
1176  const TRGClock& dClock = TRGCDC::getTRGCDC()->dataClock();
1177  ofstream output((name() + ".log").c_str());
1178 
1179  output << "Outer Superlayer Merger output dump" << endl << endl;
1180 
1181  const std::vector<int> changetime = _mosb->stateChanges();
1182  std::vector<vector<int>> boolvector(changetime.size());
1183  for (unsigned ch_t = 0; ch_t < changetime.size(); ch_t++) {
1184 
1185  for (unsigned b = 0; b < (* _mosb)[0]->size(); b++) {
1186  boolvector[ch_t].push_back(((* _mosb)[0]->state(changetime[ch_t])[b]) ? 1 : 0);
1187  }
1188 
1189  output << "# of clk: " << changetime[ch_t] << " (" << dClock.absoluteTime(changetime[ch_t]) << " ns), signal vector: " << endl;
1190 
1191  output << "Hitmap: " << endl << " ";
1192  for (int b = 0; b < 80; b++) {
1193  output << boolvector[ch_t][79 - b] << " ";
1194  if (b == 15) output << endl;
1195  else if (b == 31) output << endl << " ";
1196  else if (b == 47) output << endl ;
1197  else if (b == 63) output << endl << " ";
1198  }
1199  output << endl;
1200 
1201  for (int b = 0; b < 16; b++) {
1202  output << "PT#" << b << ": " << boolvector[ch_t][ 80 + 4 * b + 3 ] << boolvector[ch_t][ 80 + 4 * b + 2 ] << boolvector[ch_t][ 80 + 4
1203  * b + 1 ]
1204  << boolvector[ch_t][ 80 + 4 * b ] << endl;
1205  }
1206  output << endl;
1207 
1208  for (int b = 0; b < 16; b++) {
1209  output << "FT#" << b << ": " << boolvector[ch_t][ 144 + 4 * b + 3 ] << boolvector[ch_t][ 144 + 4 * b + 2 ] << boolvector[ch_t][ 144
1210  + 4 * b + 1 ]
1211  << boolvector[ch_t][ 144 + 4 * b ] << endl;
1212  }
1213 
1214  output << "Secondary: ";
1215  for (int b = 0; b < 16; b++) {
1216  output << boolvector[ch_t][ 223 - b ] ;
1217  }
1218 
1219  output << endl;
1220  output << "ET#0(63(outside 15)): " << endl << boolvector[ch_t][227] << boolvector[ch_t][226] << boolvector[ch_t][225] <<
1221  boolvector[ch_t][224]
1222  << endl;
1223  output << "ET#1(0,64(inside 0, out 16)): " << endl << boolvector[ch_t][231] << boolvector[ch_t][230] << boolvector[ch_t][229]
1224  << boolvector[ch_t][228] << endl;
1225  output << "ET#2(15,31,63,79(inside 15, 31, outside 15, 31)): " << endl << boolvector[ch_t][235] << boolvector[ch_t][234]
1226  << boolvector[ch_t][233] << boolvector[ch_t][232] << endl;
1227 
1228  output << endl;
1229  }
1230 
1231 
1232  output.close();
1233 
1234  }
1235 
1236 
1238 } // namespace Belle2
A class to represent a trigger board.
Definition: Board.h:25
A class to represent a CDC front-end board.
Definition: FrontEnd.h:37
TRGSignalBundle * _mosb
outptu signal bundle
Definition: Merger.h:136
TRGSignalBundle * _misb
Input single bundle.
Definition: Merger.h:133
TRGSignalBundle * mosb
Output signal bundle. not the best way to do this though.
Definition: Merger.h:80
unitType _type
Unit type.
Definition: Merger.h:130
unitType
enum of unitType
Definition: Merger.h:40
A class to represent a digitized signal. Unit is nano second.
Definition: Clock.h:38
A class to represent a bundle of SignalVectors.
Definition: SignalBundle.h:26
A class to represent a bundle of digitized signals.
Definition: SignalVector.h:26
A class to represent a digitized signal. Unit is nano second.
Definition: Signal.h:23
A class to represent a state of multi bits.
Definition: State.h:24
static std::string tab(void)
returns tab spaces.
Definition: Debug.cc:47
static TRGCDC * getTRGCDC(void)
returns TRGCDC object.
Definition: TRGCDC.cc:192
const TRGChannel * input(unsigned i) const
returns input channel i.
Definition: Board.h:158
double absoluteTime(int clockPosition) const
returns absolute time of clock position
Definition: Clock.cc:128
static int implementation(const unitType &type, std::ofstream &)
make a VHDL component file.
Definition: Merger.cc:66
TRGState subset(unsigned i, unsigned n) const
returns subset from i with n bits.
Definition: State.cc:356
static void unpackerOuter(const TRGState &input, const TRGState &output)
Unpack TRGState.
Definition: Merger.cc:905
const TRGClock & clock(void) const
returns clock.
Definition: SignalVector.h:125
const TRGClock & clockData(void) const
returns data clock.
Definition: Board.h:123
void dump_log_outer(void) const
dump_log for outer Merger
Definition: Merger.cc:1173
static int implementationPort(const unitType &type, std::ofstream &)
writes a port map.
Definition: Merger.cc:104
const std::string & name(void) const
returns name.
Definition: Clock.h:157
static TRGState packerInner(const TRGState &input)
Make bit pattern using input information from inner FEs.
Definition: Merger.cc:257
std::vector< int > stateChanges(void) const
returns a list of clock position of state change.
static void enterStage(const std::string &stageName)
Declare that you enter new stage.
Definition: Debug.cc:24
void dump_log(void) const
Dump all the details of _mosb into a .log file, do it in the end of simulate()
Definition: Merger.cc:1092
unitType type(void) const
return type.
Definition: Merger.cc:59
const TRGState & set(unsigned position, bool state=true)
sets state at bit i.
Definition: State.h:305
const TRGClock & dataClock(void) const
returns the data clock.
Definition: TRGCDC.h:982
virtual ~TRGCDCMerger()
Destructor.
Definition: Merger.cc:48
TRGSignalBundle * signal(void) const
returns signal.
Definition: Channel.h:93
static TRGState packerOuter(const TRGState &input)
Make bit pattern using input information from outer FEs.
Definition: Merger.cc:460
static int level(void)
returns the debug level.
Definition: Debug.cc:67
void dump_log_inner(void) const
dump_log for inner Merger
Definition: Merger.cc:1102
static void leaveStage(const std::string &stageName)
Declare that you leave a stage.
Definition: Debug.cc:34
static std::string version(void)
return version.
Definition: Merger.cc:53
void dumpCOE(const std::string &fileName="", int start=0, int stop=0) const
makes coe output.
void simulate(void)
simulates firmware.
Definition: Merger.cc:155
void push_back(const TRGCDCFrontEnd *)
push back TRGCDCFrontEnd of this Merger
Definition: Merger.cc:143
static void unpackerInner(const TRGState &input, const TRGState &output)
Unpack TRGState.
Definition: Merger.cc:719
TRGChannel * output(unsigned i) const
returns output channel i.
Definition: Board.h:165
void dump(const std::string &message="", const std::string &pre="") const
dumps contents. "message" is to select information to dump. "pre" will be printed in head of each lin...
Definition: Merger.cc:149
Abstract base class for different kinds of events.